【作者】 黄宇浩；

【导师】 吴家铸；

【作者基本信息】 国防科学技术大学 ， 软件工程， 2010， 硕士

【摘要】 嵌入式处理技术的快速发展,给高性能嵌入式系统的高速互联方面带来了严峻的挑战。为了应对这类挑战,同时适应嵌入式系统的发展需要,业界领先的半导体和系统制造商联合制订了一种可实现任意拓扑和点对点操作、高效且具有很高可靠性和有效拥塞控制的高速互联协议--RapidIO。作为目前世界上第一个、也是唯一的嵌入式系统互连国际标准,RapidIO互连架构通过定义一种高性能包交换互连技术有效地消除了系统互连瓶颈。文中从多个方面对新一代高速互连技术—RapidIO串行物理层中的物理编码子层(PCS层)进行了研究,具体如下:1.首先对串行RapidIO协议结构进行了深入研究。串行RapidIO协议分为三层,逻辑层、传输层、物理层。这种三层体系结构的最大优点是,在任意层对事务类型进行修改都不会影响到其它层的规范,具有很强的灵活可变性。2.通过对协议结构的研究分析,本文设计了串行RapidIO物理层中的物理编码子层。实现了对包的物理层字段的封装、端口的初始化、包的发送和接收、流量控制、错误管理等操作。分析了循环冗余校验码的原理并予以实现。研究了8B/10B编解码的原理并予以实现。3.设计了物理编码子层中的缓存模块,该模块解决了物理层和逻辑层之间的数据传输问题,并且实现了协议所必须的接收端流量控制功能。4.完成了串行RapidIO物理编码子层以及缓存模块的RTL级代码设计与功能验证。验证结果表明发送通路、接收通路以及错误管理功能正确,实现了协议所要求的接收端流量控制功能,符合串行RapidIO1.3协议标准,为开发和研制新一代用于嵌入式数字信号处理芯片的高速串口打下了良好基础。更多还原

【Abstract】 The fast development of embedded processing technology is posed a serious challenge to high-performance embedded system high-speed interconnection. In order to cope with such challenges and meet the needs of embedded system development, the industry’s leading semiconductor and system manufacturers work together to set up a high-speed Internet Protocol--RapidIO. The RapidIO interconnect architecture, the first and only international standard at the system interconnect level, eliminates this bottleneck by defining a high-performance, packet-switched interconnect technology.This paper analyzes the new generation high-speed interconnect technology--RapidIO physical coding sublayer of serial physical layer.from various aspects, the main results are as follows:1. First of all, this dissertation carries out study on the structure of Serial RapidIO protocol. Serial RapidIO protocol is divided into three layers: logical layer, transport layer, physical layer. Such a three layers structure characterized by a layer of affairs in any type of change will not affect other layers of the norms is highly flexible and variable.2. Based on results of the RapidIO protocol analysis, this dissertation does logic implementation of the serial physical layer’s physical coding sublayer. These logics achieve,i.e,complete the physical layer packet field encapsulation、in charge of port initialization、sending and receiving packets and control symbols、flow control、error management and other operations. This dissertation analyzes theory of cyclic redundancy check and does logic implementation of it. This dissertation analyzes theory of cyclic redundancy check and does logic implementation of it. This dissertation analyzes theory of 8B/10B codec and does logic implementation of it.3. This dissertation does logic implementation of the buffer module in physical coding sublayer. This module resolves problem of data transfer between logical layer and physical layer, and carries out the function of receiver-controlled flow control which protocol requires.4. After the accomplishment of the serial RapidIO physical coding sublayer and buffer module design and logic implementation, this dissertation does RTL simulation immediately for the implementation of the logic code. Throughout the physical coding sublayer simulation of the sending channel, receiving channel, error management function and flow control function, it verifies that the functions are correct inaccordanced with the RapidIO 1.3 protocol version. Lay a good foundation for developing new generation high-speed serial port of embedded digital signal processing chips.更多还原