【作者】 侯法柱；

【导师】 彭楚武；

【作者基本信息】 湖南大学 ， 控制科学与工程， 2010， 硕士

【摘要】 在图像采集处理系统中,实时性要求往往是系统的重要性能。本文在分析研究视频图像的处理技术及方法的基础上,应用嵌入式系统设计和图像处理技术,提出了一种以FPGA芯片作为处理器的嵌入式并行视频图像数据处理系统的设计方案。本文主要研究的内容有：1.分析研究了视频图像数据采集方法,设计了图像采集的软硬件系统,在硬件电路上,设计了图像采集卡,并通过工2C总线对图像采集卡的工作模式进行配置,在采集模块的控制下,把采集到的图像存到SRAM中。在软件设计上,采用模块化的设计方法,将系统划分为异步FIFO模块、图像空间转换模块、显示接口控制模块、SRAM存储控制模块、图像预处理模块等几个组成部分,较好地解决了图像采样存储、处理的问题,并为以后系统功能的扩展奠定了良好的基础。2.分析研究了线性与非线性滤波几种图像处理算法,在比较了几种滤波算法优缺点的基础上,提出一种适合于FPGA的快速图像中值滤波算法,并给出该算法的硬件实现结构图,运用VHDL硬件描述语言编程实现,仿真结果表明,这种快速中值滤波算法的处理速度较之传统算法有很大的提高,有效地增强了图像处理系统的实时性。3.研究了基于视频的图像检测算法,重点讨论了背景差分法。利用背景差图像直方图统计的方法确定二值化的阈值,并对图像进行二值化。结合嵌入式系统处理技术,在FPGA系统上利用VHDL语言设计实现了这些算法,并对各个模块及相应算法做了功能仿真和性能分析。4.系统仿真和验证是整个FPGA设计流程中非常重要的步骤,在现有仿真工具中,若手动设置仿真输入波形不仅工作量大而且效率低。针对这一缺点,本文采用了一种VHDL测试台(test bench)方法解决系统输入源仿真问题,使用TEXTIO程序包设计了Matlab与FPGA仿真软件的接口,很好地解决了系统仿真测试中因测试向量大而难以手动输入的问题。并将系统的仿真结果数据导出在Matlab上还原为图像,方便了系统测试结果的分析与调试。本文利用FPGA的并行处理和流水线技术,研究与设计的视频图像采集与处理系统占用系统资源少,处理速度高,实时性能的,具有较好的实用价值和推广应用前景。更多还原

【Abstract】 In the image acquisition and processing systems, real-time requirement is often an important performance of the system. This paper applies embedded system design and image processing technology and presents a FPGA chip as the processor’s embedded parallel video image data processing system design on the base of the analysis of video image processing techniques and methods.In this paper, the study includes:First, this paper analysises the video image data acquisition methods, and designs image acquisition hardware and software system. On the hardware circuit, this paper designs the image acquisition card, and through I2C bus on the mode of image acquisition card configuration, under the control of the acquisition module, the images are deposited in the SRAM. In software design, this paper applies modular design, the system is composed of asynchronous FIFO model, image space converting module, SRAM imaging storing control module, image pre-processing module. It resolved the problems such as image sampling store and processing.Second, this paper analysises some of the linear and nonlinear filtering image processing algorithms. A fast image median filtering algorithm is proposed in the paper based on the advantages and disadvantages of those filtering algorithms. it is provided that fast median filter on FPGA for image low-level processing and its hardware structure diagram, then realizes it by VHDL language. The results show that this fast median filter can lower the system resources share and promote system speed, enhance real-time performance.Third, research based on the video image detection algorithm, focusing on the statistical background subtraction method, image binarization. Using VHDL language implements them on the FPGA, and made functional simulation and performance analysis.Finally, system simulation and verification is a very important step in the FPGA design flow. If manually set the simulation input waveform, it will be a heavy workload and low efficiency. In this paper, VHDL test bench and TEXTIO package are used to resolve this problem. It can be a good solution to this problem. The test bench output the simulation results, and then display in the Matlab.In this paper, it make use of FPGA’s parallel processing and pipelining technology, research and design the video image acquisition and processing system of occupying less system resources, high speed, real-time performance and it has practical value and application prospect.更多还原