【作者】 邹海燕；

【导师】 田辉； 康桂霞；

【作者基本信息】 北京邮电大学 ， 电路与系统， 2010， 硕士

【摘要】 近年来,第四代移动通信系统在国际上受到广泛关注。我国也启动了FuTURE计划以及Gbps重大项目对4G移动通信系统的关键技术进行研究。LDPC(Low Density Parity Check,低密度奇偶校验)码以其优异的性能、简洁的形式及良好的应用前景日益吸引了广大研究人员的注意。本文的主要任务就是完成高性能的LDPC译码器FPGA(Field Programmable Gate Array,现场可编程逻辑门阵列)实现设计。本文的主要研究内容概括如下：基于对BP(Belief Propagation,置信传播)算法和LLR BP(Log-Likelihood-Ratio Belief Propagation)算法的理论分析,研究了结构化LDPC码的UMP BP_based(Uniformly Most Powerful Belief-Propagation-Based)算法。该算法考虑Gbps系统实际工程应用,采用了分层消息传递机制,并简化了校验节点译码操作。仿真结果表明,该算法性能与BP算法相当,可降低运算复杂度及存储空间,是一种能较好兼顾性能与实现复杂度的译码算法。接着提出一种高吞吐量、低复杂度、可扩展的LDPC准并行译码结构及其实现方案,针对不同码长的非正则结构化LDPC码可进行相应扩展。基于UMP BP-Based译码算法,通过优化常用的部分并行译码结构,同时对两个数据块进行操作,充分利用了硬件资源,并由此提高了译码器的吞吐量。利用Xilinx公司的Virtex-5 SX95t FPGA实现结果表明：该译码器在采用18次迭代情况下信息吞吐量可达344.9MbpS。LDPC码技术具有广阔的应用前景。本文结合LDPC码和OFDM(Orthogonal Frequency Division Multiplexing,正交频分复用)系统进行了研究,希望可以对下一步的研究工作起到积极的作用。更多还原

【Abstract】 Recently, the 4th generation (4G) of mobile communication system has received wide attention in the world. China also launched the "FuTURE" and "Gbps" program for the research on the key technologies of 4G Low-Density Parity-Check (LDPC) codes is a hot candidate channel code technology in 4G systems. LDPC has very attractive properties:error performance approaching Shannon limits, easy description and implementation, convenient theoretical analysis and research, easily decoded in complete parallel ways and suitable for hardware implementation. This thesis focuses on the LDPC decoder design in mobile communications system.The research concerns in this thesis are as follows:Based on theoretical analysis of Belief Propagation (BP) and Log-Likelihood-Ratio Belief Propagation (LLR BP) decoding algorithms, Uniformly Most powerful(UMP)BP_based decoding algorithm for structured LDPC codes is discussed with consideration of hardware implementation in 4G systems. UMP BP_based decoding algorithm can achieve performance which is very close to the BP algorithm’s performance, while the computational complexity and memory requirement are greatly reduced. Besides, in UMP BP_based decoding algorithm the convergence property as layered BP decoding algorithm is remained. So UMP BP_based decoding algorithm is an advanced algorithm that can offer trade-offs between performance and complexity.Then Low-density high-speed reconfigurable decoding architectures are proposed with the field programmable gate array (FPGA) implementation of irregular structured low density parity check (LDPC) codes. The enhanced semi-parallel decoding architectures are easily scalable and reconfigurable for different block sizes. Based on the UMP BP-Based (Uniformly Most Powerful Belief-Propagation-Based) algorithm, this thesis optimizes the common components of parallel decoder structure for two different code words at the same time. Thus, the throughout of the decoder is increased. The FPGA implementation results on Xilinx FPGA Virtex-5 SX95T show that the irregular LDPC encoder can achieve a maximum (source data) decoding throughput of 344.9 Mbps at 18 iterations.LDPC has wide application foreground. This paper studies the LDPC decoder in OFDM system. Hopefully, it is beneficial to the further research work.更多还原