【作者】 吴强；

【导师】 蒋朝根；

【作者基本信息】 西南交通大学 ， 信号与信息处理， 2009， 硕士

【摘要】 随着通信和网络技术的飞速发展,各种嵌入式系统都对设备内部的数据传输速率提出了更高的要求。传统的分级共享总线结构已达到了极限性能,互连技术问题已经成为制约嵌入式系统整体性能提高的瓶颈。面对这些挑战,一些基于点对点交换式高性能总线互连结构应运而生,而RapidIO系统互连技术正是其中的佼佼者,它最适合用于高性能嵌入式系统内部互连。RapidIO属于系统内部互连技术,是一种新型高性能、低引脚数、结构灵活、基于报文交换的点对点互连体系结构,广泛应用在连接多处理器、存储器阵列、DSP阵列、网络设备中的存储器映射I／O器件、以及通用计算平台。而4x模式的串行RapidIO,简称SRIO (Serial RapidIO),是本论文的研究重点。SRIO1.3协议的物理层支持1.25GHz、2.5GHz、3.125GHz三种信号速率,持续的全双工数据带宽范围最高可达到4Gbps到18 Gbps。本文在深入研究了串行RapidIO1.3互连协议三层体系结构中逻辑层和传输层的基础上,对这两层的功能做了一些改进。并且着重对逻辑层和传输层进行了FPGA (Field Programmable Gate Array)逻辑设计,包括实现多种事务请求包和响应包的封装和解析、各层之间的接口时序转换、多通道轮询调度,以及各层内部寄存器维护等功能。然后搭建了TCL自动化功能仿真平台和上板FPGA验证平台,对逻辑实现的Verilog代码进行RTL级仿真和上板验证。最后根据功能仿真时序波形图和实际上板所测结果分析,该逻辑层和传输层的逻辑设计在灵活性、可靠性、可扩展性方面都有非常良好的表现,完全可以封装为成熟的RapidIO软核嵌入到各种通信和网络系统之中。更多还原

【Abstract】 Due to the rapid development of the communications and network technology, various Embedded systems have higher requirement for transfer rate of data in device. Traditional hierarchical shared bus architecture has already come to its extreme performance, and the technical aspects of interconnection has become a serious problem limiting the improvement of Embedded performance. Facing these challenges, some high performance interconnect bus structures, based on point to point and exchange function, come into being. And RapidIO system interconnect technology is the top one.RapidIO is a technology within the system interconnect. It is point to point interconnect architecture with New high-performance, Low Pin Count, Structural flexibility and based on packet switching, and is widely used to connect multi-processor, Memory Array, DSP Array, Network devices in the memory-mapped I/O devices and Universal Computing Platform. Then 4x mode SRIO(Serial RapidIO) which supports three Baud including 1.25GHz、2.5GHz、3.125GHz and persistent Full-duplex data bandwidth from 4Gbps to18 Gbps, is important point of this papers.This paper has simplified the function of Logic and Transport Layer, based on in-depth study for Serial RapidIO interconnect protocol three-tier architecture such as Logic Layer, Transport Layer. The key research is FPGA(Field Programmable Gate Array) logic design for Logic and Transport Layer including the functions such as accomplishing encapsulation and analysis for a variety of services request packets and response packets, interface sequence change of each layer, the fair polling for multiply channels and maintenance of each layer’s registers. Verilog program of the design has been offered to RTL simulation and verification by building TCL platform of automated functional simulation and verification environment based on FPGA. Finally, analyzing from timing simulation waveform and measured results from verification environment, logic design of this logic and transport layers all have good performance on flexibility, reliability and expansibility, and can be packed to be a mature RapidIO soft core to be embedded into every communication and network system.更多还原