【作者】 邵文威；

【导师】 王祖强；

【作者基本信息】 山东大学 ， 电路与系统， 2010， 硕士

【摘要】 先进音视频编码标准(AVS)是我国自主研发制定的关于数字电视、IPTV等音视频系统的基础性数字音视频编解码标准。AVS标准第2部分(AVS-P2)是高效的第二代视频编码技术,其实现方案简洁,并拥有与H.264近似的压缩性能。AVS标准的编码效率得到了极大的提高,其运算复杂度也大大增加,另外实际应用环境中对实时运算的限制,这都对视频解码器的硬件的实现提出了很高的要求和巨大的挑战。本文深入研究了AVS标准,详细分析了可变长解码算法、逆扫描、反量化和反变换算法,提出了适用于AVS视频解码标准的可变长解码模块、反量化模块和反变换模块的硬件架构。可变长解码模块通过桶形移位寄存器、优化压缩查找表索引等方法以及并行和复用技术的应用,达到设计的高速、低开销。在反量化模块的设计中,反量化运算与之前的逆扫描模块中两个乒乓RAM共同节省了处理时间。反变换模块通过模块复用,实现了一种新颖的流水线结构的一维整数反变换核的运算与设计,在大大节约硬件资源的同时,也明显提高了速度。设计采用自顶向下的设计方法,运用Verilog硬件描述语言完成了可变长解码模块、反量化模块和反变换模块的RTL级建模,以参考模型RM52j为基础建立了正确的C_modeL。使用SystemVerilog语言结合高级验证方法学(AVM)搭建验证平台对设计进行了功能验证,采用事务级的验证策略,使用了随机约束和功能覆盖率等验证技术新特性。使用该验证平台能够极大的提高验证效率,并且其组件具有可重用性。应用Mentor公司的仿真工具ModelSim对三个模块进行功能仿真。采用中芯国际(SMIC)的0.18μm工艺库,用Synopsys的Design Compiler进行逻辑综合,并采用了合适的综合策略和优化手段。综合和验证结果表明,上述三个模块的设计均达到了本课题要求的目标。更多还原

【Abstract】 Audio Video coding Standard(AVS), independently developed and owned by China, is a fundamental standard in digital TV, IPTV and other audio/video based systems. AVS Part2, the video part, defines the highly efficient second generation video coding technology. Its implementation is simple and easy. Moreover, it has coding performance close to H.264. Although the coding efficiency of the AVS is better than previous standards, for some real-time applications, the complicated computational characteristics lead great challenges for today’s VLSI implementation.Based on analysis of Advanced Coding of Audio and Video Standard deeply, especially variable length decoding, inverse scan, inverse quantization and inverse transformation, this paper introduces the design of variable length decoder, and inverse quantization and inverse transformation. Variable length decoder uses the Barrel-Shifters and optimizes the look-up table index to meet a higher speed and a lower overhead and also reuses some modules in order to reduce the cost of hardware. Inverse quantization and two ping-pong RAM in inverse scanning module together save the processing time. A novel pipeline structure of the 1-D inverse transformation implementing way introduced in this paper is extremely low-cost and high-speed.In whole design, the Top-down design method is used. The design is described in Verilog HDL and a software reference model is made based on RM52j. According to Advanced Verification Methodology, testbench is constructed to functionally verify the design by using SystemVerilog, which uses transaction-level strategy, constraint-random and coverage driven methodology. The testbench improves the verification efficiency and reusability. Function simulation has been completed on each module by using ModelSim. Based on appropriate strategy of synthesis and method of optimization, three modules are synthesize by using SMIC 0.18μm CMOS technology library.The verification and simulation results all indicate that the design of the three modules has achieved requirement.更多还原