【作者】 李卓研；

【导师】 杨银堂；

【作者基本信息】 西安电子科技大学 ， 集成电路系统设计， 2010， 硕士

【摘要】 研究和发展高速、低功耗、面积小的高速模数转换器对于无线局域网、通讯系统和雷达等应用领域的系统芯片设计来说是具有非常重要的意义。折叠内插结构模数转换器由于在速度、分辨率、功耗和芯片面积等方面具有良好的特性而成为了近年来的一个研究热点。本文采用折叠内插结构,研究设计了一款基于标准CMOS工艺、1.8V电源电压、10位分辨率、1V差分输入范围、采样速率为100MS/s的高速模数转换器。具体电路设计中,负责A/D转换器整体结构分析和子A/D转换器模块的功能和性能的分析和设计。在以提高系统性能为目标和降低噪声对有用信号的影响、抑制失调误差的思路下,对关键模块进行优化,显著提高了系统的性能。设计了一个全差分带离散型共模反馈的高速采样保持电路;在预放大器、折叠放大器、子A/D转换器前端加入分布式T/H电路,有效隔离了各级的噪声;在预放大器的两边采用了冗余单元来减小边界效应;在预放大器输出、折叠器输出、子A/D转换器输出采用电阻内插的环形平均技术使邻近放大器的输出相互作用,并利用信号的奇对称性消除内插边界效应的影响,改善了系统的DNL和INL;此外,对电阻内插产生的误差机理建立数学模型进行深入分析,提出了消除误差的三种方法思路,并给出了电路实现;对三种内插方式进行了研究,从电路实现和对系统性能的影响角度比较了三种内插方式的特点。论文采用SMIC 0.18μm1P6M工艺,设计了一种10位100MS/s折叠内插流水线结构A/D转换器,并进行版图实现。整个ADC系统DNL最大为0.6LSB,INL最大为1.8LSB;在16MHz正弦波输入下SNR为50dB,SNDR为48dB,ENOB为7.8,功耗为120mW。整个A/D转换器有效芯片面积为1.6×1.6mm2。更多还原

【Abstract】 The research and development of analog-digital converter with high speed, low power consumption and small proportion is very significant in the application fields of WLAN, communication system and radar. With the nice features in speed, resolution, power consumption and proportion, folding and interpolating analog-digital converter becomes a study hotspot in recent years.This research employs the folded interpolated structure to design a high-speed analog-digital converter with 1.8V power supply, 10bit resolution, 1V input range and 100MS/s sampling rate by the use of standard CMOS process. In the circle design, this thesis is about the analysis and design of the whole ADC structure analysis and functions and performance of sub-ADC modules. By the thought of improving the system performance, reducing the impact of noise to the signal and restraining maladjustment error, to optimize key modules significantly improves the system capability. A high-speed sampling hold circuit that is fully-differential circuit with discrete CMFB is located; a distributed T/H circuit is inserted at the front end of preamp preamplifier, folding amplifier and sub-ADC to effectively insulate noises; dummy units are applied on the sides of preamp preamplifier to reduce the boundary effect; resistance interpolation by circular averaging network is located on the output terminals of preamp preamplifier, folding amplifier and sub-ADC to urge interaction between the terminals and remove interpolation boundary effect by odd symmetry of signals, which ameliorates DNL and INL of the system; besides, mathematical model is created based on the error by resistance interpolation and deeply analyzed, and three methods, which are brought forward to remove errors, and circuit structure is suggested; in the thesis, three interpolating methods are compared by the circuit structure and system performance.This paper design a 10bit 100MS/s ADC adopts SMIC 0.18μm 1P6M process. The maximum DNL is 0.6LSB, the maximum INL is 1.8LSB. At 16MHz sampling frequency input, the SNDR is 48dB, ENOB7.8. The effective area of chip is 1.6×1.6mm2.更多还原