【作者】 鲍奇兵；

【导师】 张玉明；

【作者基本信息】 西安电子科技大学 ， 集成电路系统设计， 2009， 硕士

【摘要】 随着电子技术的发展,集成稳压器成为各种电子设备中不可或缺的组成部分,线性稳压器由于具有极低的自有噪声和较高的电源抑制比,结构简单等优点得到广泛使用,为适应宽电压工作环境的需要,现在越来越多的芯片已经集成了低压差线性稳压器。本文针对一款GPS射频芯片,设计了集成于射频芯片内部的LDO。由于射频芯片中各个模块对电源噪声很敏感,所以需要降低LDO的输出噪声并提高LDO的电源抑制比,而LDO的噪声和电源抑制比很大程度上由基准电压源决定,通过在基准电压源的输出串联一路RC低通滤波器,可以有效降低LDO的输出噪声,并提高LDO的电源抑制比。RC滤波器的大电容可以外接,这样可以节省芯片面积,加大电容值可以显著的降低基准电压源的输出噪声。为了降低射频芯片的功耗,设计有开关电路,在电路闲置期间将芯片的电源关闭。由于要集成于射频芯片内部,所以对芯片面积有严格的要求。本设计输入电压范围2.6V-3.6V,输出电压1.8V,电路包括带隙基准电压源、误差放大器、缓冲器、调整管、反馈网络、过温保护电路以及限流保护电路。射频芯片正常工作电流为15mA,故设计最大输出电流50mA;负载电流在0mA到50mA间变化时,LDO输出电压变化峰值小于5mV;PSRR在1kHz处达到73.7dB,在1GHz的带宽内PSRR最小为36.6dB;在100kHz处LDO的输出噪声密度为33.5 nV /Hz ,在1MHz处输出噪声密度达到8.72 nV /Hz。本设计的版图面积约为280μm×150μm,使用TSMC 0.18μm射频和混合信号CMOS工艺实现,并成功流片。更多还原

【Abstract】 With the development of electronic technology, integrated voltage regulator is an indispensable part of a variety of electronic equipment. Linear regulator has been widely used, as it has very low noise, high power supply rejection ratio and simple structure. More and more chips are integrated with low dropout linear regulators, for it can provide a stable power supply voltage.This thesis presents the design and implementation of an on-chip low dropout linear regulator, which is integrated into a GPS radio-frequency chip. Modules in RF chips are very sensitive to the noise of power supply voltage, so it’s necessary to reduce the LDO output noise, and increase the PSRR. The noise and PSRR of LDO is dominated by the bandgap reference.To reduce the intrinsic noise and increase the PSRR of the LDO, the bandgap reference with an RC low pass filter can be adopted,and an outside capacitor is available for the RC low pass filter, which can largely reduce the output noise and increase PSRR of the LDO. In order to reduce the power consumption, a switch is adopted to shutdown the LDO when the GPS radio-frequency chip is free. This LDO is designed to have a maximum output current of 50mA,as the GPS radio-frequency chip has a 15mA current consumption,and its layout area should be the smaller the better .The simulation results shows that the maximum output variation is smaller than 5mV at a full current change from 0mA to 50mA,the PSRR of this LDO is 73.7dB at the frequency of 1kHz,and more than 36.6dB in all frequency bands, the output noise is 33.5 nV /Hz @100kHz and 8.72 nV /Hz @1MHz, and the layout area is 280μm×150μm.This LDO is fabricated in TSMC 0.18μm mixed-signal process.更多还原