【作者】 李秋芳；

【导师】 殷福亮； 陈喆；

【作者基本信息】 大连理工大学 ， 通信与信息系统， 2009， 硕士

【摘要】 回波抵消器是消除通信系统中电学回波和声学回波的功能单元。回波抵消器在免提电话、无线产品、IP电话、ATM语音服务和电话会议等系统中,都有着重要的应用。回波抵消理论及应用一直是国际上研究的热门课题之一。在不同应用场合对回波抵消器的要求并不完全相同。本文主要研究应用于电话系统中的电回波抵消器。电回波是由于语音信号在电话网中传输时由于阻抗不匹配而产生的。电回波抵消器可以生成一个模拟的回波信号,再从近端信号中减掉该模拟信号,从而实现电回波的抵消。传统回波抵消器主要是基于通用DSP处理器实现的,这种回波抵消器在系统实时性要求不高的场合能满足回波抵消的性能要求,但是在实时性要求较高的场合,其处理速度等性能方面已经不能满足系统高速、实时的需要。现代大容量、高速度的FPGA的出现,克服了上述方案的诸多不足。用FPGA来实现数字信号处理可以很好地解决并行性和速度问题,且其灵活的可配置特性使得FPGA构成的DSP系统非常易于修改,测试和硬件升级。本文的目的是在FPGA芯片上实现回波抵消器,在整个系统的实现过程中,主要完成的工作有:(1)深入研究了回波抵消器各模块算法,包括自适应滤波算法、远端检测算法、双讲检测算法,并实现了这些算法的C程序。(2)深入研究了回波抵消器基于FPGA的设计流程与实现方法,并利用硬件描述语言’Verilog HDL实现了各部分算法。(3)在QuartusⅡ集成环境下对该系统进行模块级和系统级的功能仿真、时序仿真和验证,并在FPGA硬件平台上实现了该系统。(4)根据ITU-T G.168的标准和建议,对设计进行了客观测试。更多还原

【Abstract】 Echo Canceller is a function cell which cancels electric echo or acoustic echo in communication systems. In many systems, such as handfree telephone, wireless production , IP telephone, ATM speech service, telephone conference and so on, echo cancellation technique has its important application.For the various solution of echo canceller are different, this thesis is focused on electric echo canceller applications in PSTN. Electric echo is caused by the impedence mismatch during the transmission in PSTN. Electric echo canceller can synthesize a replica of the echo and subtract it from the real echo according to reference signal.Echo canceller is usually implemented on DSP processor.Such echo canceller can meet performance of echo cancellation on the occasion which requires low real-time quality. But when the request of real-time is high, the performance such as processing speed can’t meet real-time realization. FPGA with large capacity and high speed can overcome the deficiencies as mentioned above. Using FPGA to implement digital signals processing can resolve the problem about parallel and speed. The characteristic of nimble disposition make the system easier to modify, test and promote.In this thesis, Echo Canceller is implemented on FPGA. The main accomplished task of this theis concludes the following parts:(1). Research_all modules of adaptive echo canceller including adaptive filter, far detector, double talk detector, and then implement them using C language.(2). Research flow of designing and implementation methods, all parts of algorithms is completed in Verilog HDL.(3). The whole system is functional and timing simulated in QuartusⅡenvironments, and implemented in FPGA hardware platform.(4). According to ITU-G.168, this echo canceller gets kinds of testing. All the testing achieve desirable requirement.更多还原