【作者】 孙添平；

【导师】 刘政林；

【作者基本信息】 华中科技大学 ， 微电子学与固体电子学， 2007， 硕士

【摘要】 本文首先简述了锁相环的历史、发展与应用,紧接着论述了电荷泵锁相环的基本原理,并对锁相环的相位噪声的相关理论进行了介绍和对比,最后本论文设计了一个三阶电荷泵锁相环电路,并对该锁相环进行了详细的模拟。该锁相环主要用于LVDS中的时钟产生模块,其输出频率为10MHz到160MHz,采用了七级延迟单元,由于它的七个输出相位差固定,因而可以用于高速LVDS中。设计中采用了自顶向下的方法,对电荷泵锁相环电路采用的设计思路是:从系统级开始研究,并逐步过渡到晶体管级的模块设计。首先,对电荷泵锁相环采用连续时间近似和线性近似得出了一个线性连续的相位域传输函数模型。同时为了验证所设计的电荷泵锁相环,本文建立了包括电荷泵锁相环非线性本质和离散时间特性的行为模型,并且进行了仿真验证。其次,在确定了模块的指标后,利用HJTC的0.18μm Mixed-Mode and RFCMOS工艺,对每一个模块进行了详细的设计与模拟,包括压控振荡器(VCO)、鉴频鉴相器(PFD)、电荷泵(Charge Pump)、低通滤波器(LPF),并且提出了两种方法对VCO的相位噪声进行优化。最后,将模块组合成为系统后,分析了系统在不同的工艺、温度和电源电压下的工作情况,从模拟结果可以看出,各个模块以及整体锁相环电路的设计均达到了设计要求。本论文的研究成果对于锁相环电路的系统设计与模块设计,包括相位噪声的分析与模拟均有很好的指导意义和参考价值。更多还原

【Abstract】 The paper describes the history, development and application in briefly, then, analyzes the basic principle of the charge pump PLL. It also introduces and compares some theories of PLL’s phase noise. The paper gives a design of third order CPPLL and analogs it in detail. This PLL referred there is used in LVDS clocks, whose output frequency is from 10MHz to160MHz. It can be used in high speed LVDS system because the inter VCO has 7 order delay cell with 7 phases output standThe design method of Top to Down is used, which is from the system level design of charge pump PLL to the transistor level design of each block in PLL. Firstly, we get a linear continuous phase domain transfer function model by regard the charge pump PLL as a continuous and linear system. In the meantime, In order to prove the charge-pump phase-locked loops at the system level, the paper establishes a behavioral model in simulink. The behavioral model includes nonlinearity and discrete-time nature of charge-pump phase-locked loops, and then the behavioral model is used to simulate charge-pump phase-locked loops at the system level. Secondly, after each block’s specification is decided, detailed design and simulation of these blocks are completed including Voltage Controlled Oscillator (VCO), Phase Frequency Detector (PFD), Charge Pump, Low Pass Filter (LPF), based on the 0.18μm Mixed-Mode and RFCMOS process technology of HJTC. In the meantime, two methods are used to improve the phase noise of VCO. Finally, the charge pump PLL system consisted by these blocks is simulated under different process, temperature and power voltage. From the simulation results, each block and the whole PLL system have obtained the design specifications.The achievement of this paper will provide lots of useful guides and references on the design of system and module level in PLL circuit also include the analysis and simulation of phase noise.更多还原