【作者】 高建华；

【导师】 赵毅强；

【作者基本信息】 天津大学 ， 微电子学与固体电子学， 2007， 硕士

【摘要】 随着数字电视技术的日趋成熟,模拟电视向着数字电视转变已成为必然趋势,其中视频格式转换技术起到了非常重要的作用,并蕴涵着巨大的市场价值。它的主要功能是通过数字视频信号处理将不同格式的视频输入信号转换成特定格式的输出信号。视频处理过程包括去隔行、帧频提升、分辨率提升及各种画质增强等。因此,海量数据的存储与搬移成为视频格式转换专用芯片设计中的核心问题之一,数据存储系统的优劣将直接影响到整个芯片的性能。本文从数据流调度和存取机制入手,对整个数据存储系统的实时性进行了系统的分析,并在此基础上对视频格式转换专用芯片中数据存储系统进行了研究与设计实现。重点设计了外部存储器(SDRAM)控制核,在对SDRAM存储器的工作参数分析的前提下,着重讨论了SDRAM控制器自顶向下(Top-Down)的设计方法,子模块的划分与设计,代码编写与优化、读写操作时序分析,功能仿真,逻辑综合以及FPGA调试策略,设计了一种具有高适用性的SDRAM控制器。该控制器具有标准的IP核的接口和多种可配置寄存器,可与其他模块通过简单的握手信号,完成数据的读写控制,具有很高扩展性和移植性。在完成设计的基础上,本文还介绍了SDRAM控制核和整个数据存储系统的测试验证,通过对SDRAM的单独测试和视频格式转换专用芯片整体测试,证明SDRAM控制器和存储系统完全能够达到视频格式转换专用芯片的数据处理要求。实际测试中,SDRAM控制器的工作频率达到了100MHz。更多还原

【Abstract】 As digital video technique becomes more and more widely used, the trend that analog video signal will be substituted by digital video signal is inevitable. In this interim, the video processing IC has quite a practical value and market prospect. Its main purpose is to transfer video input signals of different forms to video output signals of specific standard forms by the way of DSP. Its main functions are de-interlacing, frame rate up-conversion, scaling, quality improvement and etc. How to process and move the enormous data is one of the main problems we deal with.This thesis focuses on design and realization of the data cache system in our video processing IC. Due to the importance of the data control and write-and-read mechanism, much introduction and analysis will be put on those parts. At the same time, the real-time performance of the data cache system will also be discussed. With some critical advantages, such as small area, low cost, high speed and large volume, SDRAM becomes the ideal external memory for the video processing IC. As the basic unit, SDRAM has the responsibility of storing all the data in the video processing procedure. Therefore, the designing and debugging of the SDRAM controller is quite an important job. After carefully studying the operation of SDRAM, in this article, I focus on the design and PCB level debugging of the SDRAM controller, which include HDL coding, write-and-read timing analysis and testing. The SDRAM controller I made, which has an adaptable ability and can easily be extended to various systems, adopts handshake signals and can be directly used as an IP core.A top-down design procedure was used in the design process. Design regulation, module dividing, function simulation and synthesis are also discussed in the article. The whole device has been tested and used in the video processing system. The result perfectly met the design demand. In FPGA test, SDRAM controller is working at the frequency of 100MHz.更多还原