【作者】 刘永刚；

【导师】 朱守正；

【作者基本信息】 华东师范大学 ， 无线电物理， 2008， 硕士

【摘要】 CCSDS高级在轨系统在航天技术发挥着越来越重要的作用,而信道合路器/分路器以及虚拟信道调度策略是AOS空间站数据系统的核心,是AOS空间站能够传输多任务,高速率不同数据的关键。本文通过对CCSDS高级在轨系统(AOS)的研究,对AOS空系统的架构、特性以及业务进行了分析。信道合路器/分路器是AOS空间站数据系统的关键部分,是AOS空间站能够传输多任务,不同速率数据的关键。在对该系统的分析中,确定需传输五种不同性质、不同速率的数据(其中详查相机数据速率为150Mbit/s),并确定其传输的VCDU为4080bit。进而明确了信道合路器/分路器的功能和性能指标,以及虚拟信道调度策略需要完成任务。由于LVDS(低电压差分信号),其具有高速传输能力、低噪声、低功耗、集成能力强等诸多优点,因此确定合路器与分路器之间的数据接口标准以及其它接口之间的数据电平标准均采用LVDS电平标准。在以上工作的基础上,完成了信道合路器/分路器系统设计方案,确定了信道合路器、分路器的架构及其模块组成,插入业务的实现,数据存储器的选择,信道合路器/分路器与其它链路控制器的接口设计采用握手原则,完成数据的传输。虚拟信道调度决定VCDU在发送到物理信道时的排序,针对带有优先级的轮询的方式可能带来信道垄断的缺点,提出了加权轮询方式的动态调度策略,对其进行了分析,发现基本可以满足五种数据对物理信道的占用。以Virtex-4系列XC4VFX12型号的FPGA芯片为核心完成了系统的电路设计,用Verilog HDL语言,完成了所有的逻辑代码设计。搭建了模拟测试系统,用Tektronix TLA5201逻辑分析仪观察系统中传输的数据流。发现在大量的测试中,系统均正常工作,信道合路器/分路器可以保持合路与分路能力,数据传输流畅,无丢失现象。更多还原

【Abstract】 The CCSDS AOS plays a more and more important role in aerospace technology, while Channel Multiplexer/Demultiplexer and virtual channel scheduling become cores of AOS ISS data system, and be critical for AOS to transmit multi-services, high-speed data.Based on the study of CCSDS Advanced Orbiting System, this thesis makes analysis on AOS system structure, operational characteristics.Channel Multiplexer/Demultiplexer, the key part of the AOS ISS data system, is critical in transmitting multi-tasking data with different bit rates. In analyzing this system, the author employs 5 channels (including a detail-investigating camera with bit rate of 150 Mbit/s) to transmit various bit rates characterized signals, and the transmission VCDU is 4080 bits. After that, the channel Multiplexer/Demultiplexer’s performance is determined, as well as the task needed by Virtual Channel Strategy.LVDS(Low Voltage Differential Signal) standard is chosen to be the data interface voltage standard between the Channel Multiplexer and the Channel Demultiplexer and to be the standard of other interfaces on account of whose advantages such as high-speed transmitting, low noise, low power consumption and high integration level in related applications.On the basis of works mentioned above, a channel Multiplexer/Demultiplexe design solution has been provided, which include the architecture of the channel Multiplexer/Demultiplexer and its modules, the realization of the insert business, the selection of data memory, the interfaces design between channel Multiplexer and Demultiplexer and other link controllers based on Handshake principle for data transmitting.The method of Virtual Channel Scheduling determines the transmitting sequence when VCDU is transmitted to physical channel, and a dynamic scheduling strategy of Polling weighted approach is offered to against the disadvantage of channel monopoly caused by polling method with priority. With the work analyzed, it’s found that data’s utilization of 5 physical channels can be mostly realized.System design is completed with its core, XC4VFX12 FPGA chip,Virtex-4 series. All the logic code design is written in Verilog HDL language.A testing system using Tektronix TLA5201 logic analyzer system is built for observing data stream transmitted in system. It’s found that during the test, the system works well, channel Multiplexer/Demultiplexer are able to multiplex and demultiplex data consistently, the data stream transmits fluently without data lost.更多还原