【作者】 汪诚；

【导师】 解光军；

【作者基本信息】 合肥工业大学 ， 微电子学与固体电子学， 2008， 硕士

【摘要】 锁相环在时钟频率合成、通信同步等许多领域里都是一个非常重要的关键部件。对其在SOC芯片中的应用,尤其是在低带宽、高性能的要求场合中的研究一直是个热点和难点。本文针对传统模拟锁相环在低带宽的应用场合下有易受芯片环境噪音干扰、漏电电流大、产生的时钟抖动大、系统成本高等缺点,和传统的全数字锁相环输出频率不高和性能较差等缺点,提出了以电荷泵型高带宽的基于Σ-Δ调制器的小数分频锁相环来作为数控振荡器的全数字锁相环的思想。由于此小数分频锁相环具有很高的频率分辨率,而且它具有较高的带宽,并以晶体振荡器作为参考源,故而这种全数字锁相环可以获得很高的输出抖动性能。而此全数字锁相环的输出时钟是由小数分频锁相环中的压控振荡器直接产生,其频率上限在目前0.13微米的工艺中,可以达到几吉赫兹,完全可以满足绝大多数的应用需要。本设计在UMC 0.13微米工艺实现,其版图面积为0.2mm~2。采用cadence的混合电路仿真器进行仿真,使得整个电路的仿真时间只需一个小时左右,而且数字电路部分的硬件实现由RTL代码综合而成,从而大大减少了设计周期时间。本设计已经过流片测试,测试的结果显示这种基于小数分频锁相环作为数控振荡器的数字锁相环输出抖动RMS值为32.36皮秒,完全达到了预期设计目标。更多还原

【Abstract】 PLL is a key component in many applications such as frequency synthesizer and the synchronization of communication. It is always a research difficulties and hotspot to design a low bandwidth and high performance PLL in the SOC applications.This article describes an all-digital PLL which utilizes a fractional-N PLL as its DCO, which overcomes the disadvantages such as sensitivity to noise, charge leakage, poor jitter performance and high cost that are encountered in traditional analog PLLs, and the low output clock frequency and poor jitter performance encountered in traditional all digital PLLs as well. As the fractional-N PLL is a high bandwidth design and with a very fine frequency resolution, furthermore it uses a crystal as the reference clock, so the all digital PLL introduced in this article can achieve very good jitter performance. Its output clock frequency can be very high due to the high frequency capacity of the VCO in the fractional-N PLL.The all-digital PLL has been implemented in UMC 0.13um process. The layout area is about 0.2mm~2. In the cadence mixed-signal simulation environment, the whole all-digital PLL simulation time is less than 1 hour. The digital part circuits are described by synthesizable RTL code. Thus the whole design period can be shortened.This design has been taped-out and tested. The test results show that the output clock RMS jitter is about 32.36ps.更多还原