基于SOPC技术的弹载组合导航系统的应用研究

【作者】 龙达峰；

【导师】 沈小林；

【作者基本信息】 中北大学 ， 导航制导与控制， 2008， 硕士

【摘要】 本文研究探讨了基于FPGA的SOPC技术构建弹载导航系统方面的有关理论和技术;论文结合现代导航系统尤其是多传感器组合弹载导航系统的要求,面向工程化应用,采用大规模平台级FPGA为核心器件构建SOPC嵌入式无陀螺弹载导航系统。无陀螺捷联惯性导航系统主要由加速度计组成,该系统舍弃陀螺仪,用加速度计代替陀螺仪作为惯性测量元件,这不仅可以克服陀螺无法承受大的加速度冲击的缺点,而且系统的体积和功耗小、可靠性高等优点。使用SOPC方法在FPGA上设计嵌入式导航系统,改变了目前通用处理器、DSP+MCU(CPLD)的形式主导导航计算机设计的格局,采用软硬件协同的设计模式和可定制性更恰当的适合了组合导航系统对处理能力和接口能力的要求,具有很强的应用价值和广阔的应用前景。论文首先在分析弹体的有限空间、高动态性等特征,要求导航系统体积小、高可靠化、实时性等应用需求的基础上,结合无陀螺惯性导航理论,采用了GFSINS/GPS组合导航的导航优化方案;并从工程应用的角度出发,提出了基于IP核的SOPC技术在平台级FPGA器件上设计组合导航系统的整体方案,并给出了系统仿真验证策略和SOPC导航系统的顶层硬件结构。接下来的部分,针对弹体飞行过程中惯性导航参数的测量,论文完成了无陀螺惯性测量的硬件系统设计,包括传感器结构配置、信号调理、信号采集与处理电路的设计实现,并考虑了抗干扰等关键技术。然后,针对GFSINS/GPS组合导航系统对功能、接口等方面的要求,重点研究CPU外设的实现方案,并应用Altera的FPGA集成开发环境Quartus II及硬件描述语言VHDL,实现了ADC采样控制器、GPS接口单元等自定义逻辑电路的设计,完成对加速度传感器、GPS信号的采集、滤波和缓存,并通过对各模块仿真验证其满足设计要求。研究了导航计算机硬件板卡,包括芯片选型和硬件原理图设计;为了提高采样速度和精度,在FPGA内实现了FIR(有限冲激响应)数字滤波器的硬件设计,并通过对仿真验证其满足设计要求。最后,针对SOPC构建的嵌入式系统,其软件架构和系统初始化步骤与通用个人计算机有很大差异,应用Altera的集成开发环境SOPC Builder及IDE,完成了导航系统的NiosII构建及软件部分设计。本论文在研究基于FPGA的SOPC技术构建弹载导航系统应用方面,进行了较为全面的分析,对所设计的导航系统的各模块进行了仿真验证达到了预定的目标,证明是可行的,取得了一些有益的成果,为进一步的工程应用和开发提供了一定的基础。更多还原

【Abstract】 This paper studied has discussed based on the FPGA SOPC technology construction missile-mounted navigation system aspect related theory and the technology; The paper union modern navigation system multi-sensor combination missile-mounted navigation system’s request, face the project application, uses large-scale platform level FPGA is particularly the core component constructs SOPC embedded not to have the top missile-mounted navigation system. Gyro-free Strap down Inertial navigation System is mainly composed of the accelerometer, this system rejection gyroscope, replaces the gyroscope with the accelerometer to take the inertial survey part, not only this may overcome the top to be unable to withstand the great acceleration impact the shortcoming, moreover system’s volume and the power loss are small, reliable higher merit. Uses the SOPC method to design the embedded navigation system on FPGA, changed the present general processor, DSP+MCU(CPLD) form leadership navigation computer design pattern, uses the design pattern which the software and hardware coordinates and may have custom-made the nature more appropriate to suit the mixed navigation system to the handling ability and the connection ability request, has the very strong application value and the broad application prospect.The paper first in analyzes characteristics and so on shell body’s finite space, high dynamic, the request navigation system volume small, high reliable in the application demand and so on, timeliness foundations, unifies the non-top inertial navigation theory, has used the GFSINS/GPS combined navigation guidance optimization plan; And from project application’s angle embarking, proposed technology designs mixed navigation system’s overall plan based on IP the nucleus SOPC on the platform level FPGA component, and has given the system simulation confirmation strategy and the SOPC navigation system’s top layer hardware architecture.Part then ,In view of the shell body flight process in the inertial navigation parameter’s survey, the paper has completed the non-top inertial survey hardware system design, including the sensor structure disposition, the signal recuperation, the signal gathers and processes electric circuit’s design to realize, and has considered the antijamming and so on key technologies.Then, in view of the GFSINS/GPS mixed navigation system to aspect and so on function, connection requests, studies the CPU peripheral device to realize the plan with emphasis, and using Altera FPGA integrated development environment Quartus II and hardware description language VHDL, has realized the ADC sampling controller, the GPS connection unit and so on from the definition logic circuit’s design, completes to the acceleration instrument, GPS signal gathering, the filter and the buffer, and through confirms it to various modules simulation to satisfy the design requirements.Has studied the navigation computer hardware board card, including chip shaping and hardware schematic diagram design; In order to raise the sampling speed and the precision, has realized FIR in FPGA (limited impulse response) the digital filter’s hardware design, and through confirms it to the simulation to satisfy the design requirements.Finally, in view of the SOPC construction’s embedded system, its software construction and the system initialization step with uses in common the personal computer to have the very big difference, applies Altera integrated development environment SOPC Builder and IDE, has completed navigation system’s NiosII construction and the software part design.The present paper in the research based on the FPGA SOPC technology construction missile-mounted guidance system application aspect, has carried on a more comprehensive analysis, to guidance system’s various modules which designs carry on the simulation confirmation to achieve the predetermined goal, the proof are feasible, has made some beneficial progresses, has provided certain foundation for the further project application and the development.更多还原