射频集成低噪声放大器的分析与设计

【作者】 钟晓伟；

【导师】 陈勇；

【作者基本信息】 电子科技大学 ， 微电子学与固体电子学， 2008， 硕士

【摘要】 过去十年间,全球移动通信产业经历了前所未有的发展。CMOS工艺虽然直到最近才开始被考虑,但是如今正成为产业界的主流工艺。例如,在90nm工艺条件下,晶体管的截止频率已经高于100 GHz。这就给射频工程师提供了很多的选择余地。CMOS工艺在高频时主要的问题在于较低的跨导值以及信号通过导电率较低的硅衬底的损耗。射频集成电路的一个主要应用在于无线局域网(WLAN)。现今最流行的三个WLAN标准是IEEE 802.11a,802.11b和802.11g。802.11a标准制定于1999年,它工作于5 GHz无须申请的美国国家信息基础设施(UNII)频段。UNII频段包括两个子频段:5.15到5.35 GHz,以及5.725到5.825 GHz,两个子频段总共提供300 MHz带宽以及12个每个20 MHz的信道。本论文主要针对5.2 GHz 802.11a WLAN标准设计射频前端低噪声放大器。低噪声放大器的设计包括很多不同指标间的折衷,例如增益,噪声系数,功耗,以及输入输出阻抗匹配。关于低噪声放大器噪声以及线性度的分析将分别在第四章和第五章给出。区别于常见的幂级数分析法分析低噪声放大器线性度,这里将采用Volterra级数分析法,考虑了高频时电容以及电感的记忆性对低噪声放大器线性度的影响。最终设计的低噪声放大器噪声系数为1.35dB,输入三阶交调遮断点IIP3为7.392 dBm,增益为13.8 dB,功耗为14 mW。该低噪声放大器使用Agilent EEsof的Advanced Design System 2006A软件仿真。更多还原

【Abstract】 During the last decade, mobile communication has experienced an enormous growth. CMOS technology, which has not been considered for commercial RF applications until recently, is becoming a commercially viable manufacturing option. For example, with the 90-nm CMOS technology, transit frequencies well over 100 GHz are achieved. This offers a comfortable frequency margin for RF designers. The major problems of CMOS technology at high frequencies are the low transconductance and signal loss through the conducting silicon substrate.One of the main applications of Radio frequency Integrated Circuits is for the wireless local area network (WLAN). The three popular WLAN standards in use today are based on the IEEE 802.11a, 802.11b and 802.11g specifications. The 802.11a standard, which was ratified in 1999, operates in the 5-GHz unlicensed national information infrastructure (UNII) band. The UNII band consists of two subbands: 5.15 to 5.35 GHz, and 5.725 to 5.825 GHz, which together provide a total bandwidth of 300 MHz and offer 12 nonoverlapping data channels of 20 MHz each.This thesis focuses on designing low-noise-amplifier (LNA) for the use of 5.2 GHz WLAN. The LNA design involves trade-offs between many figures of merits, such as gain, noise, power, impedance matching, stability, and linearity. The analysis of the noise and linearity performance of basic LNA topology will be detailed separated in Chapter four and five and the design procedure will be given in Chapter six. Besides, Volterra series approach was given for the analysis of the linearity of LNA considering the memory effects of the capacitors and the inductors. The LNA achieve low NF of 1.35 dB, the input-referred third order intercept point (IIP3) of 7.392 dBm, 13.8 dB gain with 14 mW power consumption. The simulation was done with Agilent EEsof Advanced Design System 2006A.更多还原