节点文献
流水线型模数转换器的设计与研究
【作者】 武海军；
【作者基本信息】 电子科技大学 ， 微电子学与固体电子学， 2008， 硕士
【摘要】 模数转换器(ADC)是模拟信号向数字信号转换的接口电路,在现代信号处理系统中被广泛使用。流水线模数转换器由于其本身结构而具有高速高精度的优点,其功耗也较低,因此备受关注。基于对1.5位/级的流水线模数转换器工作原理和结构的研究,建立了模型并分析关键模块对结果的影响,并设计了一款10位60兆赫兹的1.5位/级的流水线模数转换器和部分模块的版图。本文工作主要包括下面四个部分:1、从流水线模数转换器的原理着手,研究了1.5位/级流水线ADC的原理和数字校正技术。采用Simulink工具分析了运算放大器和比较器的误差对结果的影响。由于流水线模数转换器结构和性能的不同,电路设计中采用的技术也不同,也详细研究了流水线模数转换器中采用的技术以及随着工艺和设计水平的提高出现的新的设计技术。2、基于SMIC 0.18μm CMOS混合信号工艺,设计和仿真了10位60兆赫兹的流水线模数转换器中的电路。设计的模块主要有:(1)带隙基准源;(2)采样保持电路;(3)乘法数模转换器;(4)运算放大器;(5)比较器;(6)自举开关。对采样保持电路和运算放大器进行了系统的分析,研究了乘法数模转换器的噪声特性和开关的导通电阻。同时设计了子模数转换器、不交叠时钟电路、延迟阵列和数字校正电路等模块。带隙基准源在TT工艺下温度从-40°到125°变化时基准电压变化1.2mV,在FF工艺下变化5.3mV。运算放大器的带宽可达400兆赫兹,相位裕度为70°。数字校正电路中的模块A+BC逻辑结构与全加器组成的校正逻辑相比具有结构简单和管子少的优点。3、进行了系统仿真,结果表明在输入斜坡信号时,几乎没有丢码;在输入2兆赫兹正弦信号,采样频率为60兆赫兹时,转换结果正确,分析结果表明无杂散动态范围为60dB,静态功耗约为200mW。4、最后合作设计了部分电路的版图,有带隙基准源、自举开关、不交叠时钟电路和触发器。在以上模块的版图设计中,需注意器件的匹配和寄生效应。分析了MOS管、电容和电阻的布局和连接方式从而达到匹配和如何避免天线效应。设计了各个模块在整个芯片中的版图布局,其中模拟模块和数字模块应分开。同时应尽量按照信号流的方向来布局。
【Abstract】 Analog to Digital Converter(ADC) is the interface circuit of the analog signal converting to digital signal and used widely in the signal processing system. Because of its high speed、low power and high presion, pipelined ADC is paid for more attention.Based on research of the theory and structure of the 1.5bit/stage pipelined ADC, the model is studied and some blocks how to affect the result are analyzed. Also, a 10bit 60MHz pipelined ADC is designed and simulated and some block layouts are designed. Four parts of our discussions included in this paper are as follows:1、From the pipelined ADC theory, the theory of 1.5bit/stage and its technology of digital error logic are researched in details. The operational amplifier and the comparator in the pipelined ADC how to affect the result are discussed using the Simulink. Because of the structure and the performance of the designed ADC, the design techniques are used differently and some new techniques are introduced with the semiconductor technics and designing technology.2、Based on SMIC 0.18μm CMOS mixed-signal model, all the pivotal circuits in10bit 60MHz pipelined ADC are designed and simulated, mainly containing: (1) Bandgap; (2) Sample and Hold circuit; (3) Muti Digital to Analog Converter(MDAC); (4) Operational amplifier; (5) Comparator; (6) Boostrapped swtich. Sample and Hold circuit and operational amplifier are analyzed mainly. The noise of MDAC and resistor of switch are researched. Also, Sub-ADC、the non-overlapping circuit、delay array and digital error logic are designed. The output voltage of the bandgap vary 1.2mV from -40°to 125°in the TT corner and 5.3mV in the FF corner. Operational amplifier’s bandwidth reach 400MHz and phase margin is 70°. The structure of A+BC in the digital error logic is new and simple and of small area compared with the one consisted of adder.3、The system simulation is done and the results show that at the ramp signal, the output of ADC do not lose code; at the sin signal 2MHz and the sample frequency of 60MHz, the output of ADC is reasonable and analyzed results prove the SFDR reaches 60dB. the static power comsumption is about 200mW. 4、Last, the layout of the some circuits are designed, containing bandgap、boostrapped switch、non-overlapping circuit and D-trigger. In the design of the layout, the device matching techniques and the antenna effect are introduced. Analog blocks and digital blocks are how to layout in the chip. The layout of all the chip should keep up with the direction of the signal.