【作者】 张桂兰；

【导师】 周伟；

【作者基本信息】 武汉理工大学 ， 通信与信息系统， 2008， 硕士

【摘要】 本文基于欧洲的DVB-T标准,对DVB-T系统接收机中的数字下变频器进行研究和设计。数字下变频器(Digital Down Converter,DDC)作为DVB-T系统数字接收机的重要组成部分,把中频的数字信号搬移到基带,有效的降低了信号的数据率,为后级基带信号处理创造了条件。在满足系统要求的前提下解决了通用芯片价格昂贵、灵活性不强且不利于整体集成的缺陷,有利于日后DVB-T接收芯片ASIC实现。本课题主要任务是设计一个能够用于DVB-T接收机的数字下变频模块。首先分析了DVB-T系统的结构和数字下变频技术的特点,研究了数字下变频的相关理论与算法,主要算法和理论是:带通采样、CORDIC算法、查表法、内插算法;其次采用自顶向下的模块化设计方法,将数字下变频器按功能划分为若干模块。并在此基础上对数字下变频的各个模块进行频谱分析和算法仿真;最后着重对数字下变频进行硬件设计与优化,采用Verilog HDL语言做为设计内部逻辑的硬件描述语言,实现了DVB-T接收机中数字下变频模块的功能仿真、测试和综合。为了便于以后ASIC实现,在设计模块时除考虑功能实现外,还要尽可能做到结构优化。在数控振荡器的设计中,给出了基于查找表(LUT)和坐标旋转矢量(CORDIC)两种算法的设计方案,改进NCO的设计,使NCO中的三角函数表资源节省了75%;在FIR滤波器设计时,采用CSD编码和系数分解法对滤波器的系数进行优化,并结合实例给出了它们的优化效果;改进传统Farrow结构内插滤波器。最后,数字下变频器在Xilinx VirtexⅡ系列FPGA器件下得到硬件实现和验证,满足系统所需的要求。更多还原

【Abstract】 This paper introduces the structure of the receiver end of DVB-T system, and discusses the study and design of the Digital Down Converter part. Digital Down Converter is a very important part of this system, it converts the IF signal into baseband, reduces the signal rate and then makes it easy for the later real time DSP operation part. Different from other traditional DDC, the architecture we desgined here can meet the needs of later DDC ASIC implementation.The purpose of this task designs the DDC that is applied to the receiver end of DVB-T system. Firstly, the related theory and algorithm of DDC are introduced. which contants CORDIC、NCO、LUT and interpolator filter. Secondly, using Top-Down design method, The DDC are divided to many function modules and organized to the module library. Meanwhile we simulate the system in Matlab, to check the system feasibility. Finally, the design method and design flow of FPGA are summarized, taking the example of Xilinx’s FPGA, and on a basis of it. we use Verilog-HDL to program the system, and implement it in the FPGA chip.In order to integrate DDC as ASIC , the paper not only focuses on realizing perform ance but on optimizing structure as well. In practice, these function modules are selected, configured and optimized to satisfy the system demand. Firstly, based on look-up table (LUT) and Coordinate Rotation Digital Computer (CORDIC) algorithm, a method for implementing a numerically controlled oscillator(NCO) is described in the paper; Secondly, the multiplier optimizing technology-CSD coding, coefficient analyze for direct structure and reduced adder graph for transpose structure, are discussed. Also the optimizing effect is presented with the examples. Thirdly, design a new structure based on the structure of Farrow in the interpolator filter.The last part of the dissertation presents system modeling, and shows the testing results.Which is proved that FPGA implementation can meet design request.更多还原