【作者】 邓鹏；

【导师】 刘章发；

【作者基本信息】 北京交通大学 ， 微电子学与固体电子学， 2008， 硕士

【摘要】 在无线通信领域中,随着GPS的不断发展,对模数转换器的性能也提出了更高的要求。模数转换器是模拟信号和数字信号之间的转换界面。在GPS射频接收机系统中,混频器降频得到的模拟信号经过模数转换器转换为数字信号送入下一级进行基带处理。通过与众多CMOS模数转换器结构相比较,流水线ADC的优越性在于保证高速工作的同时,可实现8位以上高分辨率,并且大大减少了比较器个数,从而减少了面积,降低了功耗。同时随着集成电路工艺的不断进步,对电压更低、尺寸更小的混合信号系统的研究也越显必要。因此针对上述需求,该论文完成了1.5比特/级流水线结构模数转换器的关键单元电路的研究与设计。首先,本文利用Matlab中的Simulink工具对ADC进行系统级仿真。搭建流水线ADC的系统级模块并验证了其可行性;根据分析电路中的噪声仿真得到了电容失配、运放增益误差、失调电压等因素对级间转换电路输出范围的影响;指导电路级设计采用高性能运放、版图级设计对电容匹配的关注。其次,在Cadence仿真环境中基于SMIC提供的1.8V单电源0.18μm CMOS混合信号工艺,对增益提高型运算放大器、采样保持电路、子ADC电路、MDAC电路进行研究与设计,最后给出了运放、采样保持电路的版图设计与后仿真结果。本文采用了电容翻转式采样保持电路,利用增益提高型运放的高增益与较大带宽的优点实现了10位精度、40MHz采样频率的指标要求;根据S/H电路的设计思想完成了MDAC电路的设计,并实现级间转换的功能;采用动态比较器实现了子ADC电路的功能要求。最终完成了论文设计要求。更多还原

【Abstract】 With the development of GPS receiver in wireless communication system, the high performance analog-to-digital systems are demanded. ADC is the interface between analog signal and digital signal. In the GPS system, the analog signal coming from Mixer is transferred into digital signal, and then sent to Base band. Comparing with other most ADC architecture, the pipelined ADC can achieve high speed and high resolution. Furthermore, the number of comparators will be decreased, so as to the area. Meanwhile, with the development of technology of IC, lower voltage and smaller mix-signal system is more important. In this design, we introduce the unit circuits of pipelined ADC whit 1.5 bit per stage.First, the Matlab-Simulink tool was used in ADC’s system level simulation, the model of pipelined ADC is established and proofed, the influence of offset voltage, offset capacitor and gain error to output range of pipelined stages was discussed, the high performance operational amplifier was employed in circuit design and capacitor matching was considered in layout design.Second, the circuit was designed in SMIC 0.18μm mixed CMOS technology and stimulated by Cadence Specter in this paper. The analysis and design of S/H, subADC, MDAC were presented. Finally, the and layout and post simulation are shown in this paper.The flip-flop S/H circuit with the advantages of high gain and wideband of gain-boosting operation amplifier were used to achieve 10-bit, 40MHz specifications required in the paper, the ideal of S/H was employed in the design of MDAC circuit, dynamic comparator was use in the design of sub ADC. The simulation results shown that the circuits meet the required specifications.更多还原