【作者】 王伟；

【导师】 吴强；

【作者基本信息】 湖南大学 ， 计算机软件与理论， 2007， 硕士

【摘要】 可重构计算系统利用可编程逻辑器件可重配置的特点,在通用微处理器和专用集成电路之间提供一个结合功能灵活性和高运算速度的平台,被认为是能满足未来嵌入式应用市场需求的一种极具竞争力的技术解决方案,国内外学者对此研究十分活跃。随着可编程逻辑设计技术的发展,目前的可编程器件还支持动态部分重配置,这使得可重构计算系统在运行时可以改变自身部分功能,形成一种自重构系统。这样的系统中通常包括微处理器作为主要控制器,以及若干可重构的硬件模块作为硬件加速器,因此是一个软硬件混成系统。现有设计方法在其上进行设计时,需要设计人员了解硬件接口细节,管理硬件加速器的配置,以及软硬件之间通信,这对设计人员而言比较繁琐,也容易出错,不利于提高系统设计的效率。本文提出一个硬件透明的编程模型,屏蔽了硬件接口细节,而提供一个类似软件函数的硬件函数给设计人员,使其能简单方便地使用硬件加速器。在此基础上,本文着重研究了自重构系统的实现技术及对上述硬件透明编程模型的支持。首先我们设计了在自重构系统中实现硬件透明模型的层次结构:最下层是自重构系统的硬件,硬件之上是对可重构的硬件加速器进行封装的硬件函数,最上层是支持硬件函数调用的嵌入式操作系统。然后设计了自重构系统的体系结构:把微处理器(固定部分)和所有硬件加速器(可变部分)看作一种共享存储器的异构多核并行处理结构,并讨论了它们之间的关系与实现方法。为了实现重构我们研究了自重构系统中连接固定部分和可变部分的总线结构以及实现方法。然后讨论了自重构系统设计流程,利用Xilinx提供的工具,给出了一个基于模块的自重构系统设计流程;并按照这个设计流程完成了一个包含硬件加速器及其硬件函数的自重构系统,通过实验验证了我们提出的基于硬件透明编程模型的自重构系统设计方法的可行性。实验结果表明,按照本文所给出的自重构系统设计流程,可以在单片可编程器件上实现自重构系统,在运行时根据需要把不同硬件加速器配置到可编程器件上。在硬件透明编程模型上进行设计时设计人员不用了解硬件加速器的配置和接口细节,只需要在程序中调用相应硬件函数,系统将自动完成硬件加速器配置,并控制加速器完成计算任务,极大地方便了设计工作。更多还原

【Abstract】 Reconfigurable computing using programmable hardware promises an intermediate tradeoff between flexibility and performance and becomes an impressive platform that can satisfy the requirements of embedded system applications. More recently, there has been an increasing study in the reconfigurable computing. With the development of programmable logical design technique, the programmable devices begin to support partial and dynamic reconfiguration. This provides a platform on which users can create a self-reconfigurable system that can change parts of itself at run-time. Such self-reconfigurable system generally contains microprocessor as the primary controller of the system and several reconfigurable hardware blocks as accelerators, forming a mixed software-hardware system. In the traditional method to program for such self-reconfigurable system,the programmers have to know the details of hardware accelerators, and control the configurations of hardware accelerators as well as communications between software and hardware parts. This state-of-art programming style is not efficient for system development. In this thesis, a transparent hardware-software co-design programming model is proposed. It hides the details of hardware and provides an easy-to-use interface to the programmers. How to support this transparent hardware-software co-design programming model in the self-reconfigurable system is studied.A transparent hardware-software co-design programming model for self-reconfigurable computing system is proposed. It contains three layers: a self-reconfigurable hardware system which supports the transparent programming model, the hardware functions which encapsulate the reconfigurable hardware accelerators, as well as an embedded operating system which supports the calling of hardware functions. A self-reconfigurable architecture is proposed. The microprocessor (fixed part) and hardware accelerators (reconfigurable parts) are regarded as a shared-memory heterogeneous multi-core parallel processing structure. The relation between the different parts and the implementation of the architecture are discussed in detail. The design and implementation of the bus connecting the fixed part and reconfigurable parts of the system are studied. A self-reconfigurable system design flow using Xilinx development tools is proposed. A self-reconfigurable system that contains several hardware accelerators and the corresponding hardware functions is created based on the above design flow to validate the feasibility of the proposed transparent programming model.The experiment shows that it is possible to implement a complex self-reconfigurable system in single FPGA chip based on the self-reconfigurable system deign flow discussed in this thesis. By adopting the transparent programming model, what programmers need to do is to call a hardware function while the system automatically reconfigures the corresponding accelerator and controls it to finish the computing task. This is helpful to increase the design efficiency of whole system.更多还原