【作者】 张海拓；

【导师】 周以国；

【作者基本信息】 中国科学院研究生院（电子学研究所） ， 通信与信息系统， 2007， 硕士

【摘要】 频率合成器是现代电子系统的重要组成部分，在雷达、通信、仪表和导航等领域中都有着广泛的应用。PLL是比较成熟的频率合成技术，它有杂散抑制性能好的优点，缺点是频率转换速度慢，频率分辨率不高。DDS技术以其频率切换速度快、频率分辨率高和输出相位噪声低的优点，得到了广泛的关注，但是由于其全数字的结构，存在输出带宽窄和杂散抑制差的缺点。本文将DDS和PLL技术结合起来，采用DDS直接激励PLL的混合频率合成方案完成了频率合成器的设计，通过仔细的调试，在1400MHz～1600MHz的频率范围内频率合成器工作稳定，实现了频率间隔1kHz的任意频率输出，输出信号的杂散和相噪特性良好，达到了预期的要求。本论文主要在以下几个方面进行了研究和探讨：1．分析了PLL和DDS的工作原理和特点，采用DDS直接激励PLL的混合频率合成方法，一定程度上解决了频率分辨率、锁定时间、频率转换速度和相位噪声之间的矛盾。2．采用高速的FPGA芯片完成了控制电路的设计，从而大大减小了控制字发送部分对频率转换速度的影响。3．频率合成器实现了扫频功能，有5MHz、1MHz、0.1MHz三种可选扫描步长。4．采用四阶环路完成了PLL部分的设计，对环路性能进行了理论上的推导，通过仔细的调试使PLL有效消除了DDS杂散的影响，达到了较为理想的输出频谱性能。5．对采用的混合频率合成方法进行总结，提出了进一步改善频率合成器性能的措施。更多还原

【Abstract】 Frequency synthesizer is an important component in the modern electronic systems. Ithas popular application in the field such as radar, communication, measurementinstruments and electronic navigation, etc. As a well-developed frequency synthesistechnology, PLL (Phase Locked Loop) is good at spurious behavior, but it has weaknesson frequency switch speed and frequency resolution. The DDS (Direct Digital Synthesis)technology has attracted popular attention for its excellent performance on frequencyswitch speed, frequency resolution and phase noise. However, due to its digital structurelimit, it just can work on a narrow bandwidth and its spurious level is not so good.This paper takes the DDS and PLL technologies together.A L-band frequencysynthesizer is finished with the hybrid frequency synthesis method that DDS directlydrives PLL. After a detailed debugging, the synthesizer works well from 1400MHz to1600MHz, it can output arbitrary frequency with 1kHz frequency step. The spurious leveland phase noise performance meet the requirement of actual project.The main devotement of this dissertation is as follows:1. After a detailed analysis on the basic principle of DDS and PLL technologies, thehybrid frequency synthesis method DDS directly drives PLL is adopted toovercome the contradiction between frequency resolution, lock time, frequencyagility speed and phase noise.2. Complete the control circuit with a high-speed FPGA chip. This design canweaken the impact of control circuit on the frequency hopping speed.3. Frequency sweep function is realized, and have 5MHz, 1MHz and 0.1MHz threeselectable sweep mode.4. Finish the PLL circuit with a 4th loop, several important parameters of the PLLare derived from the basic theories. After a detailed debugging, the spurioussignal generated by the DDS circuits is successfully eliminated.5. A conclusion of the DDS direct drive PLL hybrid frequency synthesis method is presented, and several useful methods to improve the performance of thesynthesizer are discussed.更多还原