高速OQPSK全数字解调器的同步算法研究与并行结构实现

【作者】 曹锦；

【导师】 杨建宇；

【作者基本信息】 电子科技大学 ， 信息获取与探测， 2007， 硕士

【摘要】 高速数字OQPSK(Offset Quadrature Phase Shift Keying)数据传输系统具有高数据率、良好的频谱利用率和抗信道非线性能力、设备体积小、重量轻、可靠性高等优点,适应全球信息化、远程多媒体通信流量剧增的趋势,可广泛应用于高速卫星通信系统和地面宽带移动通信系统。因此,对于高速OQPSK数字解调技术的研究具有重要的实际应用价值。载波、时钟同步是解调的关键环节。OQPSK调制方式I、Q两路错位半个码元的特殊性使其同步算法较传统的QPSK更复杂。针对OQPSK调制方式的同步算法已有多种,但这些算法在移动设备发射功率受限和传输距离远所导致的接收信号信噪比很低的实际应用情况下不能达到同步的要求。而且,接收的高速率调制信号是宽带信号,受信道或接收机前端模拟滤波器非恒定群时延特性影响严重,同步解调性能大大降低。另外,数字解调器的解调数据率往往受到数字器件工作速率的限制。本文将针对上述一系列问题开展了如下的工作:1.对现有数字接收机同步算法进行理论分析、仿真、性能及比较,结合本系统实际应用背景的参数要求,通过选择、综合和改进,提出了根据同步估计量自适应调整同步系统参数的同步方案,实现了适合工作在很低信噪比(可低至-2dB)情况下的OQPSK数字解调器的载波、时钟同步。2.研究信道或接收机前端模拟滤波器的非恒定群时延对宽带调制信号同步解调性能的影响,并设计数字滤波均衡器减小非恒定群时延的影响。3.研究高速数字信号处理的并行结构设计与实现方法。将解调器的同步解调算法转化为并行结构,并根据实际情况优化结构,最终实现480Mbps的高速解调。4.对数字解调器系统进行Matlab / Simulink仿真,其中包括算法理论仿真、并行结构实现仿真和定点数仿真,验证算法的有效性、并行结构的可实现性。5.完成高速OQPSK数字解调器并行同步解调的FPGA实现。主要完成同步解调各个并行模块和整体的VHDL设计和仿真。在Xilinx公司的基于芯片XC4VLX25的FPGA开发试验板上对各个模块进调试。研究结果表明,本同步解调方案和并行实现结构在性能上满足高速OQPSK数据传输系统项目设计的要求。更多还原

【Abstract】 High date-rate OQPSK (Offset Quadrature Phase Shift Keying) digital transmission, which has the advantage of high date rate, good spectrum efficiency and non-linearity resistance, compactness, and stability, adapts to the trend of global communication and the rapid growing demand for wireless multimedia communication service with long distance. It is applied broadly in satellite communication system and wide-band mobile communication system. Therefore, research about high data-rate OQPSK digital demodulation technology has important value in application.Carrier and timing synchronizations are the key process of demodulation. OQPSK modulation has a delay by half of the symbol period on the quadrature rail, which causes its synchronization scheme more difficult than conventional QPSK. There are many synchronization algorithms for OQPSK known today. But these algorithms hardly work stably and desirably under the practical condition that the SNR of received signal is very low caused by the energy constraint for mobile equipment and the long transmission distance. Furthermore, because the received modulation signal with high data rate is wide-band signal, the non-linear group delays of channel or front-end analogy filters are bad influences on synchronization and decision, reducing the performance heavily. Moreover, the date rate of digital demodulation is usually limited by the speed of digital components. To solve above problem, work of this thesis shown as follow have been done:1. Synchronization algorithms for the digital receiver known today, including carrier frequency synchronization, carrier phase synchronization and timing synchronization, are investigated broadly. Via theoretical analysis, simulation, performance compare, selection, integration, and amelioration, synchronization scheme, in which the synchronization system parameters are regulated by synchronization estimators, is proposed this thesis. It is shown that this scheme works well when the SNR of received signal is very low (as low as -2dB).2. The influence of the non-linear group delays of channel or front-end analogy filters on performances of synchronization and demodulation with high date-rate wide-band modulation signal is investigated. A digital pre-filter as the equalizer is designed to solve the problem.3. The methods of design and implement of parallel high speed digital signal processing structure are investigated. By converting synchronization and demodulation scheme into parallel structure, 480Mbps high date-rate demodulator is realized at the expense of increased hardware resource.4. This thesis validates the efficacy of the synchronization scheme and the realizable of the parallel structure, by Matlab / Simulink simulations, including theoretical simulation, simulation of parallel structure, and fixed-point simulation. This thesis also optimizes the algorithms, structure, and adjusts the parameters, based on demand of the application.5. This thesis implements the high data-rate OQPSK digital parallel demodulator by FPGA. The main works are the VHDL design and simulation of the parallel synchronization and demodulation modules and the whole. Using the Xilinx FPGA evaluation kit based on XC4VLX25, the modules are debugged.The results of the research indicate that the synchronization and demodulation scheme and parallel structure proposed in this thesis satisfy the demand of the high date-rate OQPSK digital transmission system design.更多还原