【作者】 张珂；

【导师】 虞露；

【作者基本信息】 浙江大学 ， 信息与通信工程， 2007， 硕士

【摘要】 新近视频编码标准如MPEG-4、H.264／AVC和AVS等在提高编码性能的同时算法复杂度也大大增加，使得在传统处理器上实现编解码变的困难，VLSI技术凭借其低代价、低功耗、高性能的优势逐渐成为编解码器的主流实现方式。用较短的上市时间(time-to-market)完成高性能、低硬件代价的设计是产品获得成功的根本，由此视频编解码芯片的设计方法具有重要研究意义。本文对新近视频编码标准的实现复杂度及硬件实现特点进行了分析，对系统架构、存储和算法模块三个方面的设计方法进行了重点研究，并将设计方法有效地应用在AVS编解码芯片具体设计中，实现了硬件代价优化的目标。在系统架构设计中分析了编码器编码性能、硬件代价和编码速度三者之间的制约关系及系统架构设计瓶颈，研究了编码算法对硬件实现的影响和流水线设计方法在系统架构设计中的应用。在存储设计中分析了片上存储和片外存储的特性和优化目标，研究了延时隐藏、压缩存储等设计方法在提高总线效率和存储效率中的应用。在算法模块设计中研究了硬件复用思想、速度面积平衡思想和流水线均衡思想，分析了可配置设计和利用数据统计特性实现硬件优化的设计方法。利用流水线设计方法完成了AVS编码器的混合流水架构，在保证编码性能的前提下对编码算法进行了调整，挖掘和利用了视频混合编码框架中潜在的处理并行度。利用片外存储特性设计了AVS编码器片外存储结构，实现了提高总线效率和片外存储利用率的目的；利用压缩存储思想对AVS变长解码码表存储进行了优化，相对于参考文献存储面积节省了30％。利用硬件复用思想设计了AVS帧内预测模块，通过设计可配置结构在多预测模式之间实现硬件复用。利用速度面积平衡思想设计了指数哥伦布解码器和AVS编码器残差重建模块，在指数哥伦布解码器中利用码字长度统计特性设计专用硬件结构，相对于参考文献硬件代价节省了70％；在AVS编码器残差重建模块中利用量化输出的统计特性设计了基于零预测的硬件结构，处理速度在中等质量下提高4倍左右。最后本文给出了综合应用各种设计方法的设计实例——AVS变长编码模块。在变长编码模块设计中综合使用了流水线、存储优化、硬件复用和速度面积均衡等多种设计方法实现了硬件代价优化——码表存储节省了61.5％的存储面积，指数哥伦布编码器节省了60％的硬件代价。更多还原

【Abstract】 Latest video coding standards, such as MPEG-4, H.264/AVC and AVS, are characterized by high complexity as well as compression efficiency. VLSI attracts more attention by its advantage on cost, power and efficiency. And the VLSI implementation becomes the mainstream of the video codec design. Low cost is of vital importance to video application with a great quantity, so study on the VLSI design methodologies of video codec is very meaningful.The thesis focuses on the efficient design methodologies of video codec. Based on the analysis of latest video coding standards, methodologies of architecture design, memory design and module design are studied intensively. Furthermore, these methodologies are utilized in the implementation of AVS codec, which shows high efficiency.In architecture design, tradeoff among coding efficiency, hardware cost and coding speed in encoder architecture design was analyzed. Pipeline technique was studied to exploit the parallelism of video coding algorithms. Methods of delay concealment and compression storage are studied in memory design to increase bus efficiency and storage efficiency. Hardware reuse, speed-cost joint optimization and pipeline balance design are illustrated in module design.Based on the analysis of AVS coding algorithms, a hybrid-pipeline architecture was proposed for AVS encoder. By utilizing the characteristics of off-chip memory, the frame storage organization of AVS encoder was designed. Data compression storage method was utilized in the storage of AVS Variable-Length-Coding tables and a reduction of 30% was achieved in memory cost. Hardware reuse, speed-cost joint optimization methodologies were utilized in the implementation of intra-prediction, variable length decoder for AVS with 70% reduction in hardware cost and residual reconstruction for AVS encoder with 400% speedup in medium quality.At last, variable length encoder for AVS was implemented utilizing several methodologies. Owing to the well-designed hardware architectures, the encoder achieved considerable optimization with 61.5% memory cost reduction and 60% hardware cost reduction in Exp-Golomb encoder.更多还原