【作者】 段立明；

【导师】 赵振业；

【作者基本信息】 天津大学 ， 通信与信息系统， 2006， 硕士

【摘要】 在研究数字电视制式、开发数字电视产品、监测数字电视系统运行、维修数字电视设备时,均需提供图像格式不同、扫描和编码参数不一的多种码流。因此,开发一款数字电视传输流发送和截取系统十分必要。USB接口总线以其方便、快捷等优势,得到了迅猛发展,其最新规范USB2.0更将传输速度提高到了480Mbps,使其成为PC通用标准接口之一。为此,本文在课题组已有PCI总线数字电视传输流发送和截取板卡研制工作基础上,开发了基于USB2.0的数字电视传输流发送和截取系统。在USB2.0计算机通用接口与数字电视ASI和SPI通用接口间转换,是本系统必须具备的功能。为此,本文首先详细学习和分析了USB2.0、ASI和SPI总线技术。在此基础上,为实现三者间的转换,完成了几个主要工作:USB2.0数据包的形成和处理;为解决接口间数据传输速率不匹配,采取了设置缓存器措施,研究了其控制策略;为集传输流输入/输出功能于同一板卡,较好地进行了电路的逻辑设计;解决了转换中码流的同步问题。组成系统的几个主要硬件功能模块为:1.系统主控模块:主要由CY7C68013芯片实现。CY7C68013是一款USB2.0接口芯片,利用其实现USB数据包的发送和处理,而且CY7C68013内嵌有增强型8051单片机内核,能很好的完成系统控制功能。2.时钟发生模块:主要由AD9833芯片实现。3.逻辑控制模块:由通用CPLD芯片EPM7128S实现。4.数据缓存模块:由大容量先入先出存储器IDT72V2111实现。为准确地传输码流数据,必须设计一整套有效传输数据的约定。这些约定以CY7C68013为核心实现,通过CY7C68013两个外部中断,对数据传输进行控制。在此约定之上,本文开发了系统软件。主要程序包括:CY7C68013芯片固件、AD9833芯片设置程序、CPLD程序和USB驱动程序等。开发过程中,反复进行了功能模块和系统的调试工作。本文构建了两套联调系统,一套是实时播放系统。另一套是硬盘存储系统。这两套联调系统,发现并协助解决了众多问题。目前,作为实验性能样机,系统已实现了数字电视传输流USB2.0输入/输出和不同接口间转换等主要功能,播放的码流可同步解码,连续显示,截取的大段码流无误。更多还原

【Abstract】 A variety of streams with different image forms and scanning, coding parameter are needed in some researching fields, for example :researching digital TV(television) system, exploiting digital TV products, supervising the running of digital TV system and maintaining the digital TV devices.And the interface USB has the advantage of convenience and speed, it developed very quickly. The speed of USB2.0 is as high as 480Mbps. So USB2.0 becomes one of the PC general purpose interface bus.So this project perfects and develops the digital TV transfer stream creating, analysis, error_ inspection, outputting and getting system.The transform between USB2.0 and ASI, SPI is the main function of our system. So we analyze the interface of USB2.0, SPI and ASI carefully. Through this, we discuss the possible designs of the transfer code of digital TV outputting and getting.To finish the system, we should solve several tasks: dealing with the data packets of USB2.0; setting a cache, to solve the problem of the difference of transfer speed; to the in and out system into one card, we should solve the circuit logical well; we must get the synchronous clock.The main functional modules of the system are:1. The MCU module: CY7C68013 is one kind of chips which designed for the USB2.0 interface, it can treat with the data package of USB, and there are an 8051, it can control the system very well,2. The clock output module: we chose the chip of AD9833 to finish this function.3. Logic control module: we chose the chip of EPM7128S.4. Cache module: we chose the chip of IDT72V2111. It is a FIFO.To transfer the data correctly, we must have a functional transfer protocol. The chip of CY7C68013 is the core in the protocol. We use the two external interrupt of CY7C68013 to control the data transfer. And from this protocol we finish the software part, such as the firmware of the chip of CY7C68013, setting of the chip of AD9833, the programmer of CPLD, the driver designing of the USB interface.During the developing, we do a lot of tests to perfect the system. We have two system for test, one is Real-time playing system, the other is store and play system. Through these system, we find and sovle so many bugs. Now our test card can finsh更多还原