【作者】 吴曙荣；

【导师】 杨银堂；

【作者基本信息】 西安电子科技大学 ， 微电子学与固体电子学， 2006， 硕士

【摘要】 本文详细介绍了直接数字频率合成器(DDS)的工作原理、基本结构;分析了理想频谱图,并总结出了DDS的噪声来源:相位截断误差、幅度量化误差、DAC的非线性转换误差、时钟泄漏和开关暂态引起的杂散等。并针对其特点,采用时域波形分析的方法,分析了噪声来源对DDS输出频谱的影响。其次,本文在对现有DDS技术的大量文献调研的基础上,提出了符合FPGA结构的DDS设计方案并利用MAX+PLUSII软件在Altera公司的FLEX10K系列器件上进行了实现。主要研究内容包括:1)可以实现LFM(Linear Frequency Modulation)功能的32位流水线相位累加器的设计;2)基于ROM的相位-幅度转换器的设计;3)详细地介绍了ROM存储器的各种压缩方法并提出了对ROM存储器的改进;4)详细介绍了几种降低杂散的方法,并对其中的相位抖动法进行了理论分析;5)在MAX+PLUSII软件下实现电路的时序仿真和在MATLAB语言下进行电路仿真;6)简单研究了DDS+PLL混合频率合成器;通过实验表明,使用流水线结构加法器、加法器最低位修正、相位抖动法和ROM压缩等技术,用FPGA设计的直接数字频率合成器在满足系统性能的条件下,可以减少芯片面积,提高器件的运行速度,从而降低其生产成本。更多还原

【Abstract】 In this paper, we shall introduce the structure, basic principle and ideal frequency spectrum of direct digital frequency synthesizer (DDS), and conclude some sources of output spurious signal in DDS: such as phase-truncation error, amplitude quantization error, digital to analog non-linearity error, clock leak error and switch transient error etc. Then in light of their properties, we adopt the method of time-domain waveform to analyze these influence generated by them in the output spectrum and provide the distribute pattern of their error frequency spectrum.In this work, after reviewing a lot of literatures published on DDS technology, a DDS scheme based on FPGAs’structure are proposed, and implemented in Altera’s FLEX10K series FPGAs using MAX+PLUSII tool.The research including:1) Design of pipelining 32-bit frequency-phase accumulator with LFM(Linear Frequency Modulation);2) Design of phase-amplitude converter based on sin ROM Look Up Table;3) Introduce of various ROM register’s compression methods in detail, and bring forward the improvement of ROM register’s compression;4) Present several methods about how to reduce the spurious frequency in detail, and emphasize introduce the dithering measure;5) Implement emulator under MAX+PLUSII tool and use MATLAB language to carry out circuit emulator;6) Simply study Hybrid Frequency Synthesis: DDS+PLL.The experiment shows: used pipelining structures, modify the lowest bit of frequency-phase accumulator, phase dithering measure and look-up table compression etc methods, used FPGAs to realize DDS saved chip resources while satisfy the premise of functions.更多还原