Ku波段介质稳频锁相环频率源设计

【作者】 唐军；

【导师】 杨国渝；

【作者基本信息】 电子科技大学 ， 无线电物理， 2006， 硕士

【摘要】 频率合成技术是电子系统实现高性能指标的关键技术之一。锁相技术是第二代频率合成技术,用它实现的频率合成器性能优良。取样鉴相和锁相是模拟锁相,其灵活性好,又能显著降低相噪。用介质谐振器设计振荡器(DRO)也是微波频段常用的一种频率合成技术。介质谐振器(DR)由高介电常数、低损耗的微波陶瓷材料制作而成,它能极其容易地实现微波频率源的低相位噪声。同时,DR的谐振频率温度系数可正可负,这可以大大提高DRO的频率温漂性能。本文介绍了一个应用取样鉴相和锁相原理制作的微波KU波段频率源(频率合成器),其中的压控振荡器部分是用介质谐振器(DR)设计的。DRO和取样锁相的理论分析和设计方法是本文重点阐述的内容。本文在场效应管FET栅极上加上谐振网络(谐振网络是通过CST仿真得到的,它是串联反馈回路,介质工作在TE01模,对于其后的FET,它又相当于一个带阻滤波器),然后设计输入输出匹配电路,使电路结构满足起振条件,之后继续用谐波平衡法仿真和优化,使振荡器输出功率合适,相位噪声很低。在振荡器之后,本文加了一个缓冲放大器,它起到放大输出功率和改善频率稳定度的作用。在锁相环设计中,本文让晶振参考信号激励阶跃恢复二极管,从而转换成取样脉冲。该脉冲重复频率和晶振完全一致,被直接送到取样鉴相器的门开关电路,周期性接通“开关”,当这一“开关”接通时,来自VCO的信号被送到保持电路(这叫取样),该电压一直保持到“开关”再一次接通,如此持续进行,形成误差电压。误差电压经放大后送入环路滤波器进行滤波和再放大,然后去改变变容管偏置电压,控制振荡器输出频率,达到稳频的目的。综上所述,本文为低相噪、高频率稳定度频率源的研制提供了一个可行的设计方法。更多还原

【Abstract】 Frequency synthesizing is the key technique to realize a good performance electronic system. A frequency synthesizer with very good performance can be designed using PLL. By using SPLL,a better synthesizer with lower phase noise can be realized. Dielectric resonator (DR) is often used to stabilize the frequency of an oscillator. DR is made of microwave ceramic with high dielectric constant and very low loss. Using DR, the phase noise of an oscillator could be made to be extremely low. At the same time the temperature coefficient of a DR could be positive or negative, and this may be used to compensate for the frequency drift due to temperature shift. In this paper,a Ku band frequency source based on sampling phase lock loop technique is introduced. The VCO of the loop is designed using dielectric resonator. The theory and design method is discussed and emphasized on. The resonance network is connected to the gate, then the output and input matching network is designed to satisfy the oscillation criteria. Then harmonic balance method is used to analysize and optimize the output power and phase noise. To minimize the load pulling effect a buffer amplifier is designed to isolate the oscillator and the load. In the design of the SPLL, SRD takes the input of a crystal oscillator and generate very sharp and narrow pulses. The frequency of the pulse is the same as that of the crystal oscillator. The pulses sampled the output of the VCO and generate the error signal. The error signal is amplified,更多还原