【作者】 金方其；

【导师】 严晓浪；

【作者基本信息】 浙江大学 ， 电路与系统， 2006， 硕士

【摘要】 在过去的几十年内,指令集仿真器成为了嵌入式处理器设计过程中必不可少的一部分。它在已有的计算机系统上为开发中的处理器构造一个模拟平台,验证处理器的正确性和有效性,支持目标程序的运行和调试。硬件设计者用仿真器来评估目标处理器的性能,修改体系结构中的瓶颈。系统开发者用仿真器来开发编译器和操作系统,开发和测试他们的应用程序,实现软硬件协同开发 本文研究了软件仿真器的设计方法和软硬件协同仿真的实现方法,针对自主研发的嵌入式处理器CK510,用C/C++开发了一套可配置的时钟精确的软件仿真平台,这个平台里包括时钟精确的软件仿真器,AMBA AHB总线功能模型,以及实现协同仿真的PLI接口。仿真器采用的是基于解释的仿真策略,执行驱动的实现方式,完整的建模了CPU的流水线结构、中断处理器机制。 本文所设计的软件仿真平台最大的特点在于有很强的可配置性,不仅软件仿真器的模型可以配置,而且仿真的环境也可以根据需要配置。仿真平台可以运行在C++的模型下,根据仿真的目的选择是否需要总线功能模型;也可以运行在Verilog的环境下,通过PLI接口实现协同仿真。灵活的仿真环境可满足不同用户的需求。更多还原

【Abstract】 In the last decades, instruction set simulator has became an essential development tool for the design of embedded processor. It is a simulation platform that builds on the existing computer system for an under developing processor. Designers can execute programs on these models to validate the performance and correctness of a proposed hardware design. Programmers can use this software models to develop and test software before the real hardware becomes available.This thesis studied the design methods of instruction set simulator, and the implementation of hardware-software co-simulation. We develop a software simulation platform with C/C++. This platform contains a reconfigurable cycle accurate instruction set simulator, whose target processor is CK510, an embedded processor developed by Zhejiang University. It also contains a bus function model of AMBA AHB, and a Procedure Language Interface (PLI) developed with VPI library. Our instruction set simulator is an interpretive simulator, which implements with execution driven approach. In order to get accurate simulation result, it models the pipeline architecture and exception handle of CK510 completely.The cycle-accurate simulation flat is reconfigurable. Foremost, the instrunction set simulator is reconfigurable, users can modify the cache size, associative way number, the size of branch history table, the big endian or little endian. Secondly, the environment of simulation is reconfigurable. It has a stand-alone mode with an external environment simulatied in C++. It also can simulate in Verilog mode, the C++ external environment is disabled and simulated with Verilog.更多还原