【作者】 林大隽；

【导师】 高明伦；

【作者基本信息】 合肥工业大学 ， 电路与系统， 2004， 硕士

【摘要】 PCI(Peripheral Component Interconnect)总线是近年来出现的一个面向多媒体技术的优秀总线，它凭借许多高端性能而成为PC机局部总线的首选。PCI总线接口电路的设计方法是PC机超大规模集成电路设计部门所面临的挑战性课题。 本文基于国家信息产业部项目“嵌入式32位微处理器开发及产业化”(项目编号：信运部[2001]900号)和合肥工业大学微电子设计研究所承接的设计服务项目“PCI接口信息安全芯片开发”。 论文的主要工作和取得的成果如下： 1．制定了从PCI内侧总线协议。内侧协议中包含了PCI总线接口三级缓存的考虑，三级缓存的设计提高了PCI总线接口的数据传输速度、节约了使用PCI总线的时间。 2．讨论了从PCI IP(Intellectual Property)核的设计方法。提出了基于多状态机结构的从PCI设计方法。算法级设计中还包含了异常情况下状态机软着陆、三级缓存等设计技巧，这些设计技巧对其他大型接口电路的设计有直接的借鉴意义。 3．讨论了从PCI内侧协议与符合PVCI(Peripheral Virtual Component Interface)标准外设总线的接口综合技术。提出了基于状态机的接口封装技术。 4．讨论了PCI接口AD双向总线及PCI接口读操作时序的特性。提出了PCIAD总线再复用模型。该模型不仅可以保证功能正确，而且节约了32根管脚资源，进而缩小了芯片面积、降低设计成本。 5．讨论了EPROM／EEPROM的读写时序。提出了基于状态机的参数化接口模型。 本文研究的从PCI IP软核、从PCI内侧协议与PVCI标准外设总线的接口综合技术通过了FPGA(Field Programmable Gate Arrays)功能验证。本文研究的PCI接口AD总线再复用模型、PCI接口信息安全芯片通过了ASIC(Application Specific Integrated Circuit)流片验证。更多还原

【Abstract】 PCI (Peripheral Component Interconnect) bus, which has been the first chosen in recent years for PC local bus because of its high performance, is an excellent bus for multimedia. It is a challenge for R&D department of VLSI to design a PCI bus interface.This dissertation is supported by the following projects: the project of "The Development and Commercial Usage of Embedded 32-bit MCU" from MII and the project of "The Development of Security Chip Based on PCI IP" from the Institute of VLSI Design, Hefei University of Technology.The main work and achievements are as follows:1. PCI Slave bus protocols on the inner of the PCI interface is established The inner protocol includes the consideration of three level data buffer. The design of three level data buffer will increase the data transfer speed of PCI and decrease the using time of PCI.2. The methodology of designing the PCI bus interface IP core is discussed. A design method of PCI Slave IP which based on multi-state machine structure is proposed. The measurement for transaction safety and data buffering are valid for other large interface circuit design.3. The automatic synthesis of interface between PCI inner protocol and PVCI (Peripheral Virtual Component Interface) is discussed. A design method of interfacing which based on state machine structure is proposed.4. On the base of investigating the properties of PCI address/data bus and the sequence of read, a re-use model of PCI address/data bus is proposed. The model is not only working perfectly, but also reducing the pin resource, die size and costs.5. The methodology of interfacing with EPROM/EEPROM is discussed. An interfacing model with parameter timing is proposed.The contents of the dissertation has been verified by FPGA ( Field Programmable Gate Arrays) . The model for re-use PCI address/data bus and the chip for PCI bus security have been verified by ASIC.更多还原