现代机载雷达I/O接口模块的研究与实现

【作者】 陈峥；

【导师】 赵荣椿；

【作者基本信息】 西北工业大学 ， 计算机应用技术， 2001， 硕士

【摘要】 本文描述了在以综合化、实时化和标准化为目标的前提下，一种属于嵌入式系统的机载雷达I/O接口模块的设计和实现的方法。本接口模快上具有2个RS-232接口、4个RS-422接口、1个RS-485接口、8路A/D转换接口、8路离散量接口及VME总线接口，同时带有512K容量的FLASH ROM、256K容量的SRAM和可作为数据共享与信息传输的16K容量的DPRAM存储器，处理器的工作主频在20MHz以上。依据I/O模块的功能要求和结构体系，采用功能模块化的方法，运用标准化和优化的手段，尽量应用大规模/超大规模及复杂可编程逻辑器件，建立了一个的可靠的设计方案。同时深入讨论和分析了异步通信接口码间干扰理论，并论证了造成ADC系统和VME总线系统功能失效的原因，并给出了其相应的解决措施，最后，讨论了用CPLD器件实现了一个VME总线接口控制器的方法和过程。更多还原

【Abstract】 In this paper, we introduce a solution for I/O module in avation radar system bassed on the goal of integration real-time and standard. The I/O module is also an embedded system. On this module, there are 2 interefaces of RS-232 ~ 4 interefaces of RS-422 I intereface of RS-485.. 8 channels of A/D comvertion .. 8 kinds of signal interefaces and VMEbus intereface. By the way ,there are also huge memory of 512K FLASHROM~ 256K SRAM and 16K DRAM which is used to transfer message and be as an sharing data area. The CPU is at the rate of 20MHz. To realize the functions of the I/O module, we designed a scheme by using LSTI VLSI IC and standard . optimalization and founction method. At the same time, this paper talks about the theory of UART lSl(lntemal Signal Interfere) and researchs the failure reason of the ADC system and VME bus, also it has realized a solution for overcoming.and improvement. At last, we discuss and research the method of designing a VMEbus control system on CPLD (coplicated programmable logical devices).更多还原