【作者】 郭思宇；

【导师】 赵鹤鸣； 乔东海；

【作者基本信息】 苏州大学 ， 信号与信息处理， 2013， 硕士

【摘要】 本论文的主要目的是设计适用于局部授时定位系统的同步时间信号全数字收发机，实现基于直接序列扩频通信原理的收发机中频数字信号处理。发送系统主要由基带处理单元和频带处理单元构成。接收系统主要由解调单元和解扩单元构成。整个工程用VerilogHDL语言完成所有模块的设计，通过ModelSim仿真和SignalTap验证，最后连接所有系统模块，在Altera公司的Cyclone IVE系列FPGA（现场可编程门阵列）芯片中实现。论文首先提出了一种适用于野外工作的局部授时定位系统。然后从工程的角度介绍了收发机的总体架构，通过MATLAB仿真工具设计出收发机系统参数以及所用到的滤波器系数。讨论了收发系统中各个模块的理论依据以及详细的实现方法。发送机中主要模块包括差分编码器、扩频序列发生器和NCO（数控振荡器），接收机主要模块包括Costas环、超前-滞后符号同步环、匹配滤波器以及差分解码器。所有的模块都给出了仿真波形，最后下载到Altera公司具有最新FPGA技术的DE2-115开发板上进行验证。验证结果表明整个系统工作正确，性能稳定，占用资源相对较少，完全满足设计要求。更多还原

【Abstract】 The main purpose of this thesis is to design a synchronous time signal all-digitaltransceiver for the local timing and positioning system. It is based on direct sequencespread spectrum communication principles. The transmission system mainly consists of thebaseband processing unit and the band processing unit. The receiving system mainlyconsists of the demodulation unit and the despreading unit. All modules in the entireproject are designed with Verilog HDL, simulated and verified using ModelSim andSignalTap. At last, all the modules are connected together and the entire project isimplemented in an Altera’s Cyclone IV Series FPGA (Field Programmable Gate Array)chip.First, this thesis presents a kind of local timing and positioning system which isadapted to field work. Then it introduces the overall structure of the transceiver from theengineering point of view and designs the transceiver system parameters and the filtercoefficients used in the system. This thesis also discussed the theoretical basis of thevarious modules in transceiver systems as well as detailed methods of their implementation.The transmitter includes differential encoder, spreading sequence generator and NCO(numerically controlled oscillator). The receiver includes Costas loop, ahead-hysteresisloop, matched filter and a differential decoder. The modules simulation waveforms aregiven in thesis. Finally, download the project to the Altera DE2-115development boardwhich is equipped with the latest FPGA technology to verify the design.Verification results show that the whole system works correctly, is stable, occupiesfew resources and fully satisfies the requirements.更多还原