【作者】 孙道让；

【导师】 刘蕴红；

【作者基本信息】 大连理工大学 ， 电机与电器， 2011， 硕士

【摘要】 随着FPGA (Field Programmable Gate Array)的广泛应用,其灵活的配置性能和优异的数字处理性能越来越多地被展现出来。FPGA的动态重构也已成为计算机系统研究的新热点,它可以实现对FPGA的逻辑资源分时复用,缩减大型数字系统的IC规模,有效地降低功耗。但是对于工作在恶劣环境中的数字系统所遭遇的环境变化,预先设计的功能可能无法满足环境的需要,为此本文提出一种远程动态重构的方法,对系统设计进行远程升级。本文在分析动态重构的原理和FPGA配置结构的基础上,结合Xilinx公司提供的EAPR (Early Access Partial Reconfiguration)局部动态重构的设计方法,提出了一种基于IP核的动态重构改进设计,简化了设计流程。进一步,本文提出了一种基于GPRS无线数据传输的远程动态重构的方法。使用Lab VIEW编程语言在控制中心上位机设计一个TCP服务程序,采用TCP传输方式,将FPGA重构模块的配置数据传输至现场设备的GPRS模块。单片机读取GPRS模块缓存内数据转存至配置数据存储器。FPGA通过SystemACE控制器读取数据进行动态配置。因为GPRS具有永远在线特点,可以实时进行远程动态配置。配置数据采用CF卡进行存储,因为CF卡要接受单片机的写操作和SystemACE的读操作,本文采用多路复用器进行电路设计,对CF卡进行分时复用。随着FPGA集成规模不断扩大,配置文件也越来越大,为了提高系统重新配置的效率和节省数据无线传输的时间,采用改进的游程编码将配置数据进行有效的压缩,同时也可以节约CF卡存储空间。使用Xilinx公司的XUPV2P开发板、STC89C54、MC52i和CF卡构建了一个实验系统,创建了一个动态重构工程对本文的理论进行了验证。从数据无线传输到FPGA的重构,都进行了严格监控,系统运行稳定。更多还原

【Abstract】 With the extensive application of FPGA (Field Programmable Gate Array), FPGA is well-known for its flexible configuration and excellent digital processing performance. The technology of FPGA dynamic reconfiguration has also become a research hot spot in the field of computer system. It can realize the time sharing of FPGA logical resource. It can also curtail the IC scale of large scale digital system and reduce the power dissipation effectively. But when the digital system working in severe environment confronts some environmental change the previous designed function may not satisfy the environment any more. In order to update the system design remotely, one remote dynamic reconfiguration method is proposed in this paper.After analyzing the principle of dynamic reconfiguration and FPGA configuration structure, a modified design based on IP cores is proposed in this paper combining with EAPR design method provided by Xilinx Company. Then one remote dynamic reconfiguration method based on GPRS data wireless transmission is proposed.One TCP server is built on the upper computer in the control centre by using Lab VIEW to transmit FPGA configuration data in TCP transmission mode to the GPRS module working in the field. Micro Control Unit reads the configuration data from buffer of GPRS module and then saves it to the configuration memory. FPGA reads the data via SystemACE controller to complete the dynamic reconfiguration. CompactFlash card is used as the configuration memory in this paper. Multiplexers are used in the circuit design to allow MCU and SystemACE controller time share the CF card. With the expanding of FPGA integration scale, the configuration files become larger and larger. So the configuration data is compressed using modified run length encoding, thus the time spending in data transmission and saving can be saved and the storage memory can be saved.The experiment system is built using XUPV2P development board designed by Xilinx Company, STC89C54 MCU, MC52i and CF card. A dynamic reconfiguration is built based on the system to verify the theory proposed in this paper. The process from data transmission to reconfiguration is closely monitored. The system is stable in operation.更多还原