【作者】 齐亮；

【导师】 刘剑飞； 曾祥烨；

【作者基本信息】 河北工业大学 ， 通信与信息系统， 2011， 硕士

【摘要】 随着光纤通信系统的扩容,偏振模色散(PMD)成为超长距离光传输系统的重要障碍。PMD电域补偿技术成本低,能够有效地消除由PMD引起的码间干扰,还能减小光纤非线性造成的影响,降低对光发射机与接收机性能的要求。现代FPGA芯片大多集成了支持高速乘累加(MAC)运算的DSP模块且I/O接口较多,可快速实现并行DSP算法。特别是一些高端芯片集成了可接收高速以太网信号的吉比特I/O,因此,可用FPGA来实现PMD电域均衡器。本文对LE、DFE和MLSE三种均衡器的性能进行了对比,选择MLSE均衡器来均衡10Gbit/s的IM/DD系统中的PMD信号。分析了MLSE均衡器的原理、结构及光纤信道特性,用直方图估计法作为信道估计方法,将估计结果转化为分支度量,然后用维特比译码器进行译码,译码结果作为均衡器的输出。由于光纤通信系统速率较高,为适应FPGA处理速度的要求,本文将10Gbit/s的IM/DD系统中受PMD影响的信号进行80路并行处理,即将所需的FPGA最大频率降至125MHz。并利用流水线技术将传统的MLSE均衡器改进成并行输入、并行输出的结构,以其适应并行系统的要求。MLSE均衡器在Altera(?)StratixⅡGX系列EP2SGX130GF1508C3芯片上实现,利用Modelsim软件进行仿真。仿真结果表明,所设计的均衡器性能稳定,均衡后的眼图张开高度和Q因数明显好于均衡前。更多还原

【Abstract】 With the development of optical fiber communication systems which are large-capacity ,the polarization mode dispersion(PMD)is a big limitation for long-distance optical fiber transmission systems.The compensation technology in electrical domain can eliminate the inter-sysmbol interference caused by PMD with low-cost,and reduce the effect of the fiber non-linear,it can compensate adaptively. Modern FPGA families provide more I/O port and DSP arithmetic support with fast-carry chains that are used to implement multiply-accumulates (MACs) at high speed.So the DSP arithmetic in Parallel processing systems can be implement fastly on FPGA.Especially,some advanced chip provide the gigabit I/O which is used to receive signal of ethernet at high speed,as a result,it can be used to implement PMD electrical equalizer.In this article,MLSE equalizer is selected for PMD compentation in 10Gbit/s IM/DD system by the comparision among LE、DFE and MLSE. Histogram method is used as the channel estimate method by the analysis of optical fiber channel characteristics and the theory,the structure of MLSE equalizer.The branch metrics transforming from the channel estimating result is used as the input of viterbi decoder.And result of the decoder can be treated as the output of the equalizer.For the high transmission rate of optical fiber communication systems and the low processing speed of FPGA, the signal with PMD in 10Gbit/s IM/DD system is divided to 80 channels for parrallel processing in order to reduce the maximum freqence to 125MHz.Traditional MLSE equalizer is improved to the structure with parallel input and parallel output by pipelining technology for the parallel processing system. The MLSE equalizer is implemented on the chip of EP2SGX130GF1508C3 in Altera(?)StratixⅡGX family.The simulation implement by modelsim.The result shows that the equalizer is in stable performance,and the eye diagram height is obviously better than that before equalizing,as well as the Q factor.更多还原