【作者】 许玉婷；

【导师】 喻明艳；

【作者基本信息】 哈尔滨工业大学 ， 微电子学与固体电子学， 2010， 硕士

【摘要】 信号同步算法集中了GPS软件接收机的主要运算量,其完成的主要功能是接收GPS中频输入信号,从中解扩解调出GPS卫星的导航电文用于后续的定位解算。同步算法主要包括捕获和跟踪二个阶段,捕获阶段通过三维搜索得到可见卫星号及其粗略的C/A码码偏和载波多普勒频偏;跟踪阶段通过修正频偏和码偏产生与接收信号同步的本地信号,从而将载波和C/A码从输入信号中剥离,得到最终的导航电文。二个阶段中的相关器是实现实时软件接收机的瓶颈。作为ASIC和通用处理器之间的折中,专用指令集处理器(Application Specific Instruction Set Processor,ASIP)兼具了专用性和灵活性。本文研究了GPS信号同步算法,并根据其运算特性,基于Nios II嵌入式处理器实现了面向GPS同步算法的ASIP,同时把显式通信指令集结构的TRIPS作为另一ASIP的备选方案,基于其指令集对部分同步算法做了汇编优化。最后对二种方案的ASIP性能进行了分析和比较,探索了基于ASIP的GPS信号同步算法的嵌入式实时解决方案。本文通过对捕获和跟踪算法的分析,确定了核心运算单元FFT/IFFT和Bit-Wise相关器为主要待优化单元,继而从二个单元中提取出了一组专用指令,进行了基于Nios II的指令扩展,从而完成了ASIP的Nios II实现,并对其做了板级验证。同时,为了在TRIPS上获得更好的性能,对FFT/IFFT和Bit-Wise相关器二个核心运算单元做了TRIPS汇编优化。最后提取二种ASIP的性能参数分别进行了分析,并使用归一化的频率对二者进行了比较。通过分析二种方案的ASIP性能参数,发现虽然基于Nios II的ASIP已经获得了相对较优的性能,但使用显式通信指令集的体系结构(TRIPS)在处理GPS信号同步算法时的优势更加明显。更多还原

【Abstract】 As the main operation unit of GPS software receiver, signal synchronization arithmetic receives intermediate frequency input signal, and then obtains navigation data from it through dispreading and demodulation for following positioning unit. Signal synchronization arithmetic can be briefly divided into two phases, acquisition and tracking. Acquisition gains visible satellite number、cursory phase of the C/A code and cursory Doppler frequency shift of carrier by three-dimensional search; Tracking generates local signals which synchronized with input signals through adjusting the C/A code and Doppler frequency shift, so that C/A code and the carrier can be removed from input signals and the navigation data can be extracted. The correlators in the two phases are performance bottlenecks in implementing real-time GPS software receiver.As a trade-off between ASIC and general-purpose processor, Application Specific Instruction Set Processor (ASIP) possesses both specificity and flexibility. Signal synchronization algorithm of GPS is studied in this paper. According to its characteristics, ASIP of GPS signal synchronization algorithm based on Nios II embedded processor is implemented. At the same time, TRIPS with Explicitly Communication ISA architecture is proposed as another option of ASIP, and part of the signal synchronization algorithm is optimized through implementing with TRIPS assembly language based on its instruction set. At last, two ASIPs proposed are evaluated and compared, which explores the embedded real-time solution of ASIP-based GPS signal synchronization algorithm.Based on the analysis of acquisition and tracking algorithms, FFT/IFFT and Bit-Wise correlator are the key operation units of the GPS software receiver. This paper takes both of them as the main units to optimize, from which a set of specific instructions was extracted, and an exploration of Nios II-based instructions was made, then the ASIP is implemented in the Nios II IDE and verification was completed on a FPGA test-bed. Besides, TRIPS assembly optimization for FFT/IFFT and Bit-Wise correlator was made in order to achieve better performance. Finally, we extracted and analyzed performance parameters of the two realizations of ASIP, and compared them using normalized frequency. By analyzing performance parameters of the two ASIPs, we found that the ASIP based on Nios II had comparatively good performance, but TRIPS with Explicitly Communication ISA architecture put up better performance.更多还原