一种用于MCU的低功耗电源系统设计

【作者】 卢昌鹏；

【导师】 周锋； 刘华；

【作者基本信息】 复旦大学 ， 集成电路工程， 2011， 硕士

【摘要】 电源管理是电子系统不可或缺的一部分,随着工艺尺寸的不断缩小,片上系统的迅速发展,它也在朝着高集成化的方向发展。将电源管理电路与需要供电的模块集成在同一块芯片上不仅可以减小芯片面积和引脚数,降低系统成本,还可以降低模块间的串扰和寄生损耗,提高系统性能。本文对不同电源电路的优缺点进行了比较,并提出了适合于MCU应用的电源系统方案。本文设计的电源系统由两部分构成,分别为待机模式电源电路和正常工作模式电源电路。前者是一个带有输出缓冲级的超低功耗准电压基准源,主要用于保证待机模式下芯片中部分存储器和低频振荡器的正常工作；后者是一个低压差线性稳压器,主要用于保证正常工作模式下芯片中MCU、各种存储器、高频振荡器及I/0口的正常工作。芯片在正常工作模式时,低压差线性稳压器被唤起,为芯片提供内部电源电压；芯片在待机模式时,低压差线性稳压器停止工作,由准电压基准源电路为芯片提供内部电源电压；这样可以达到降低芯片平均功耗的目的。基于HEJIAN 0.25μm CMOS工艺对电路进行设计与仿真,待机模式电源电路的静态电流为240nA,最大输出电流为100μA,输出电压为2.1V,精度为±0.15V,最大温度系数为110ppm/℃,电路的线性调整率和负载调整率分别为13mV/V和2.2mV/μA,低频时电源抑制比为-44dB。正常工作模式电源电路的静态电流为135μA,最大输出电流为20mA,输出电压为2.4V,精度为±0.1V,最大温度系数为36ppm/℃,电路的线性调整率和负载调整率分别为8.3mV/V和-0.24mV/mA,低频时电源抑制比为-56dB,1MHz时电源抑制比为-34dB。更多还原

【Abstract】 Power management is an essential part of the electronic system and is moving in the direction of high integration with the continuously shrinking of the feature size and the rapid development of system-on-chip (SoC). Integrating the power management circuitry and the blocks needing regulated supply voltage on a single chip can not only reduce the chip area and pins and lower the cost of system, but also reduce the crosstalk between them and improve the performance of the system.In this thesis, the advantages and drawbacks of different power circuits are compared and the scheme of power system suitable for MCU application is proposed. Power system designed here consists of two parts, namely, standby mode power circuitry and active mode power circuitry respectively. The former is an ultra-low power quasi-voltage-reference with an output buffer stage, mainly used to guarantee part of memories and the low-frequency oscillator of the chip to work normally in standby mode; the latter is a low dropout regulator (LDO), primarily used to ensure MCU, kinds of memories, high-frequency oscillator and I/O ports to work normally in active mode. When the chip is in active mode, LDO is aroused to provide the internal supply voltage for the chip; when the chip is in standby mode, LDO stops working and the quasi-voltage-reference provides the internal supply voltage for the chip; this can lead to lower average power consumption of the chip.Based on HEJIAN 0.25μm CMOS technology, the two circuits have been designed and simulated. The quiescent current, the maximum output current, output voltage, accuracy and the maximum temperature coefficient of the power circuitry used for the standby mode is 240nA, 100μA,2.1V,±0.15V and 110ppm/℃respectively. Its line regulation and load regulation are 13mV/V and 2.2mV/μA, and its power supply rejection ration (PSRR) is -44dB at low frequency. The quiescent current, the maximum output current, output voltage, accuracy and the maximum temperature coefficient of the power circuitry used for the active mode is 135μA, 20mA,2.4V,±0.1V and 36ppm/℃respectively. Its line regulation and load regulation are 8.3mV/V and -0.24mV/mA, and its PSRR is -56dB at low frequency and -34dB at 1MHz.更多还原