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符合WLAN 802.11a/b/g/n标准无线收发机中混频器的研究

Design of the Mixers for WLAN 802.11a/b/g/n Transceivers

【作者】 蒋颖丹

【导师】 赖宗声;

【作者基本信息】 华东师范大学 , 微电子学与固体电子学, 2011, 硕士

【摘要】 随着平板电脑、智能手机、电子书等手持式移动通信设备的日益普及,以及Internet应用程序和电子商务的快速发展,用户需要随时连接到高速无线网络。在无线局域网领域,新的技术和标准层出不穷,一方面,为了实现多种标准间相互兼容,灵活切换,多模多频WLAN终端不断发展;另一方面,WLAN信道情况愈加恶劣,对收发机射频级电路的设计提出了更为苛刻的性能指标要求。本文基于0.13μm CMOS工艺,设计了可支持IEEE 802.11a/b/g/n四种标准,应用在WLAN收发机的混频器电路,包括5-6GHz和2.4-2.5GHz两个频段的正交上、下混频器。本文取得的主要成果如下:(1)在对IEEE 802.11a/b/g/n无线局域网标准充分研究的基础上,分析了WLAN收发机的系统架构并对其中混频器模块的性能指标提出设计要求;(2)提出了一种正交有源下混频器结构(申请专利:互补折叠式射频正交CMOS下混频器,201010190546.X),可分别支持WLAN 802.11a和802.11b/g/n标准。该结构基于折叠形式的吉尔伯特结构,互补跨导级采用电流复用技术提高增益,开关级采用电流注入技术降低噪声,片上集成输入阻抗匹配网络,成功实现了线性度、增益、噪声性能之间的折衷;(3)研究了一种堆叠型正交吉尔伯特上混频器结构,可分别支持WLAN 802.11a和802.11b/g/n标准,重点分析了其中跨导管、电流注入管尺寸和直流偏置电流对上混频器增益、线性度性能的影响。片上集成输出阻抗匹配网络,方便与后级射频功率放大器或者射频测试仪器级联使用;(4)采用0.13μm RF CMOS工艺流片,对所设计的混频器芯片进行了功能和性能测试。2.4-2.5GHz正交下混频器转换增益约为4dB, IIP3达5dBm,噪声系数11.2dB; 2.4-2.5GHz正交上混频器转换增益大于3dB,OP1dB在4dBm左右,噪声系数13dB; 5-6GHz正交下混频器转换增益在5.5dB以上,ⅡP3达到11dBm,噪声系数12.8dB; 5-6GHz正交上混频器转换增益可以达到3dB, OP1dB约为2.5dBm,噪声系数17dB,满足802.11a/b/g/n收发机系统性能指标的要求。本论文研究受“核心电子器件、高端通用芯片以及基础软件产品”国家重大专项中《嵌入式多模、多频收发器关键IP核研究》项目(项目编号:2009ZX01034-002-002-001-02)资助。

【Abstract】 With the growing popularity of the handheld mobile communication devices, such as tablet PCs, smart phones, e-books, and the rapid development of Internet applications and e-commerce, users need to connect to a wireless network at any time. In the field of wireless LAN, there are emerging new technologies and standards. On one hand, only multi-mode multi-band terminals can be used to realize flexible and convenient communication; on the other hand, the worse case of the wireless channel, makes more demanding performance requirements of the RF circuits in transceivers.In this thesis, a chip of mixers which applied in wireless LAN transceivers is designed and fabricated in 0.13μm CMOS process. The up/down conversion mixers cover 5-6GHz and 2.4-2.5GHz bands, and support IEEE 802.11a/b/g/n standards. The main achievements are shown as follows:(1) Based on thorough study of the 802.11a/b/g/n high-speed wireless LAN standards, the disadvantages and advantages of typical transceiver configuration are analysed, and detail design specifications of the mixers are given.(2) A quadrature down conversion active mixer structure (patent NO. 201010190546.X) is presented, which supports 802.11a and 802.11b/g/n standards respectively. The topology is based on the folded Gilbert mixer. Current-reuse techique is added in the complementary transconductance stage to enhance the conversion gain. Current bleeding technique in the switch stage decreases the noise figure. An on-chip input impedance matching network is also included. It realizes the trade-off among linearity, conversion gain and noise figure successfully.(3) A stacked quadrature up conversion active Gilbert mixer, which supports 802.11a and 802.11b/g/n standards is studied. The influence of the transconductance transistor sizes and bias currents on the mixer performance are analysed. An on-chip output impedance matching network is included to be cascaded with PA and RF measurement equipments.(4) The chip is achieved on 0.13μm RF CMOS process. The measurement results are shown as follows:for the 2.4-2.5GHz down-mixer, conversion gain is 4dB, NF is about 11.2dB, and IIP3 is about 5dBm; for 2.4-2.5GHz up-mixer, conversion gain is above 3dB, OP1dB is about 4dBm, and NF is 13dB; for the 5-6GHz down-mixer, conversion gain is more than 5.5dB, IIP3 is as high as 11dBm, and NF is about 12.8dB; for the 5-6GHz up-mixer, conversion gain is as high as 3dB, OP1dB is about 2.5dBm, and NF is about 17dB. The results meet the specifications requied by the transceiver absolutely.This thesis’work is supported by project "Key IP cores design for the embedded multi-mode multi-band transceiver" under the state key item of "core electronic devices, high-end general chips and basic software product" (Project number: 2009ZX01034-002-002-001-02).

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