【作者】 姜波；

【导师】 张尔扬；

【作者基本信息】 国防科学技术大学 ， 信息与通信工程， 2008， 博士

【摘要】 目前,中继卫星高速数据传输技术是无线通信技术研究的热点之一,也是发展我国空间信息网络必须解决的关键技术之一。论文结合两套高速调制解调器的研制展开研究,内容包括两个方面:(1)宽带正交调制信号的载波同步技术;(2)DRSS信道的非线性均衡技术。论文第一部分研究了宽带正交调制信号的载波同步技术。基于最大似然估计理论推导并总结了几种正交调制信号的载波参数估计的克拉美罗限,从而确立了衡量载波参数估计性能的基准;提出了改进的差分前向频偏估计算法,提高了频偏估计的精度、增大了估计范围;在详细分析判决指导一阶、二阶DPLL性能的同时,给出了参数设计方法;分析了载波相位误差对正交相干解调的影响。上述内容为宽带正交调制信号的载波同步设计提供了理论依据。论文第二部分研究了DRSS信道的非线性均衡技术。首先,结合实际链路建立了DRSS信道的非线性模型,分析了非线性的影响。其次,仿真分析了用户星HPA的非线性预失真(预均衡)和中继星转发器系统的非线性预失真,给出了改进的无记忆和有记忆非线性预失真方法,仿真结果表明“非线性预失真+功率回退”可以有效补偿DRSS信道的非线性失真。然后,从非线性均衡(后均衡)的角度补偿DRSS信道的非线性失真,重点研究了基于稀疏Volterra滤波的非线性均衡。为了快速构建稀疏Volterra均衡器,提出一种改进的遗传算法;为了提高稀疏Volterra均衡器的收敛速度,提出一种改进的QRD-RLS算法;分析了有限精度下Volterra滤波的量化效应。仿真结果表明非线性均衡能够有效消除DRSS信道的非线性ISI。在这部分的最后一章,研究了非线性降秩均衡技术,首次将多级维纳滤波技术引入到Volterra滤波中,提出了非线性均衡的降秩滤波算法,显著减少了自适应训练的采样支撑;进一步给出Volterra滤波器的一种流水线结构,有效减小了计算量。论文第三部分论述了相关的工程设计。完成了300Mbps TCM-8PSK信号的载波同步设计,完成了800Mbps 8PSK信号的盲均衡设计,并在FPGA上实现;结合工程实践给出一种有效的高速数字解调器的调试方法。更多还原

【Abstract】 Recently, high rate data transmission technology in DRSS becomes an active research field in wireless communication, and is one of the key problems of our country’s spatial information systems. Research was carried out grounded on the design of two high speed modems. Two main subjects were discussed in this thesis: the carrier synchronization for broad-band quadrature modulation signals and the nonlinear equalization for the DRSS channel.In the first section, the thesis investigated the carrier recovering techniques for broad-band quadrature modulation signals.Based on the ML estimate theory, several CRBs of carrier parameters for quadrature modulation signals were deduced and concluded. These CRBs act as a measurement for evaluating the carrier recovering algorithms. An improved difference feed-forward frequency estimate algorithm was presented, which increased the precision and the range of frequency estimation. The performance of first order decide directed DPLL and second order decide directed DPLL were analyzed in detail, and the methods of carrier parameter designing were also given. At last, the influences of carrier phase errors on coherent demodulation were analyzed and simulated. The research above offers a theoretical basis for the carrier recovering module design.In the second section, the thesis investigated the nonlinear equalization techniques for the DRSS channel.Firstly, Aiming at the actual links, the nonlinear models for the DRSS channel were described, and the influences of nonlinear on the system performance were analyzed.Secondly, nonlinear pre-distortions, namely pre-equalizations, for the HPA in user satellite and for the transponder system in relay satellite were analyzed and simulated, and improved nonlinear pre-distortion methods were presented. The simulation results show that the scheme combining nonlinear pre-distortion and power back-off is efficient to compensate the nonlinear distortion in the DRSS channel.Thirdly, nonlinear equalization, namely post-equalization, for the DRSS channel was studied. Nonlinear equalization based on sparse Volterra filter was especially investigated. An improved genetic algorithm for constructing the sparse Volterra filter was proposed. An improved QRD-RLS adaptive algorithm was presented, which increases the convergent speed for the sparse Volterra filter. Furthermore, the quantified effects on the Volterra filter was analyzed. The simulation results show that the nonlinear equalizer removes the nonlinear ISI in the DRSS channel effectively.In the last chapter of this section, the reduced rank nonlinear equalization was studied. MWF was introduced to the Volterra filter for the first time. A reduced rank algorithm for nonlinear equalization was proposed. The new algorithm reduces the samples for training the equalizer greatly. Furthermore, a pipeline implementation for the Volterra filter was presented, which reduces the computation complexity of the Volterra filter.In the third section, a carrier recovering module for 300Mbps TCM-8PSK demodulator and a blind equalizer for 800Mbps 8PSK demodulator were designed and realized in FPGA. Furthermore, an efficient debug method for high speed digital demodulator was proposed and used in practice.更多还原