【作者】 易志强；

【导师】 王匡；

【作者基本信息】 浙江大学 ， 通信与信息系统， 2006， 博士

【摘要】 数字电视正逐步取代模拟电视成为新兴的信息产业之一,即将掀起新的经济浪潮,而数字电视芯片又是数字电视的核心。随着VLSI工艺技术以及EDA工具的发展,数字电视应用需求的不断增长提高,数字电视芯片的功能和规模也在相应地增加,集成度和复杂度越来越高,单芯片、一体化已然成为当今数字电视芯片发展趋势。本文主要开展了针对有线数字电视SoC芯片系统算法与结构的设计研究。对信道解码解调部分的算法选定、芯片系统中各个功能部件的软硬件协同设计方案、系统任务调度安排以及片上总线设计等几个方面进行了分析和探讨,并给出最终解决方案和研究结果。本文主要内容安排如下:第二章基于软硬件协同设计的方法、过程以及技术,提出一种适合有线数字电视SoC芯片设计的软硬件协同设计策略。按照SoC设计层次化的设计理念,在最粗颗粒度级上根据划分准则进行系统结构划分,力求降低信道与信源模块之间的耦合性,方便设计的同时也便于将来对系统进行扩展和更新。第三章对芯片中信道解码解调部分进行研究,针对DVB-C标准,对影响接收性能的载波恢复、定时恢复、均衡器等关键功能模块的算法进行分析讨论,并确定实现方案。按照SoC芯片设计策略,根据算法流程对信道子系统进行架构设计和划分。结合软硬件协同设计思想,对各个功能模块的实现方式进行分析研究。给出结论。针对芯片内管理控制子系统的功能特点,提出采用基于ASIP的软硬件协同方法的实现手段。给出ASIP设计流程,完成指令集制定、硬件结构设计以及代码汇编器设计,并给出软件工作流程。第四章对芯片中信源解码部分进行研究,按实现功能分为系统层解析、音频解码、HDTV视频解码和新一代多媒体应用四个部分。在不同颗粒度级层次上,对各个任务从实现目标、运算复杂度等方面进行分析,并结合系统实时性、灵活性以及整体性的要求,确定了各个任务及其子任务的软硬件实现方式,给出高效的解决方案,以满足实时性要求和降低实现成本。其中,在多媒体处理部分,以MPEG-4视频解码为例,分析其软件实现的运算代价,给出软件实现流程以及优化手段。针对任务本身以及各类微处理器内核的功能特点、提出采用RISC+DSP双核体系架构,以同时满足媒体处理对实时性和灵活性的要求。第五章针对有线数字电视SoC芯片中主要任务进行分析,通过任务映射将系统任务分解为主控处理器任务和视频软硬解码任务,并根据任务特点以及系统要求制定出适当的调度策略,确定调度粒度、优化实现结构和任务处理流程。在总线设计上,分析总线任务的带宽需求。制订出多总线架构方案。对带宽需求最大的系统总线采用位宽不同的双总线架构,并提出静态时分复用与动态固定优先级相结合的系统总线仲裁机制。通过分析媒体处理系统任务特征,确立集中式仲裁架构。设计出基于核心仲裁器的调度架构以实现系统总线与局部总线之间的数据流通。最后是全文总结和工作展望。更多还原

【Abstract】 The digital television (DTV) is replacing the analog television to become a new information industry gradually, and it will eventually raise a new high economic tide. The IC chips for DTV is critical. As the development of VLSI technology and EDA tools, the incessant increasing requirement of DTV application, the scale of chip and functions are also increasing accordingly, the integration and complexity are more and more higher. Single-chip and integration have already been the trend of DTV chip development currently. This paper mainly focuses on the research and design about architecture and algorithm of cable-DTV SoC chip, analyses and discusses the channel demodulate/decode algorithm, the hardware/software co-design of each function part, system tasks schedule and On-Chip Bus (OCB) design. Finally, provides the solution and research result. The structure of this paper is arranged as follows.In the second chapter, a hardware/software co-design tactic which adapts to cable DTV SoC chip has been proposed, based on the method, process and technic of hardware/software co-design. In term of the idea about hierarchical design for SoC, the system architecture partition at the most coarse granularity has been taken. The partition weakens the coupling between channel modules and source modules, is convenient for design and system extension or update in the future.The third chapter focuses on the research about channel demodulate/decode part. Under DVB-C standard, analyses and discusses some module which affect the performance of receiver critically, such as carrier-recover, timing-recover and equalizer, provides the implement scheme. According to the tactic of SoC design, the channel sub-system has been partitioned and structured by the algorithm flow. With hardware/software co-design idea, analyses and researches the mode of each function module implementation. According as the function characteristic of manage sub-system, proposes hardware/software co-design method based on ASIP, provides the design flow of ASIP, completes the instructions set, hardware architecture design and code assembler design, also provides the software execute flow.The fourth chapter researches the source part in the chip. According to the function, the source part can be partitioned four sub-parts, which are system-level parsing, audio decoding, HDTV video decoding and multimedia application. At various granularity level, analyses each task by its implement aim and operation complexity. Also considering the real-time, flexibility and integration, decides each task and sub-task implement mode, provides the high efficiency solution, meets the real-time requirement and decreases the cost. Thereinto, in multimedia process section, usingMPEG-4 video decoding as illustration, analyses the operation cost of software mode, provides the software implant flow and optimizing technique. According as the characteristic of tasks themselves and MCUs, proposes "RISC+DSF" double-core architecture, in order to meet real-time and flexibility requirement.The fifth chapter analyses the main task in cable DTV SoC chip. Through task mapping, the task has been divided into master processor task and vide decoding task. According to the characteristic of task and system requirement, makes the proper schedule scheme and granularity, optimizes the structure and process flow. For the OCB, through analyzing the bus bandwidth requirement, proposes the multi-buses architecture. Especially for the system bus whose bandwidth requirement is most critical, adopts double-bus architecture. Each sub-bus of system bus has different bitwise. Proposes a static time division multiplexed with dynamic fixed priority arbitration scheme. Through analyzing the characteristic of media process task, establishes centralized arbitration architecture. Provides a schedule structure based on kernel arbitrator to realizing the data transaction between the system bus and local bus.The last chapter is the summary of this paper and the perspective of the future work.更多还原