【作者】 罗春；

【导师】 时龙兴；

【作者基本信息】 东南大学 ， 微电子学与固体电子学， 2006， 博士

【摘要】 验证已成为系统芯片(SoC)设计所面临的重大挑战,形式验证所能验证的电路规模远远不能满足设计需要,基于仿真的验证方法一直占统治地位。课题主要研究基于仿真的SoC验证技术。首先,提出并实现一种向量自动生成算法——“基于遗传算法和覆盖率驱动的Verilog RTL功能验证向量自动生成算法”。反馈覆盖率信息构建闭环系统,采用遗传算法根据覆盖率模型分析覆盖率信息自动生成验证向量。然后,提出并实现一种故障模型——“Verilog RTL域故障模型”。域故障模型准确全面地反映导致域错误的原因,域覆盖率衡量验证工作的充分性,域测试点选择策略快速生成域测试所需测试点。接着,实现基于C参考模型和SVA(System Verilog Assertion)的功能检查方法。最后,提出并实现一种SoC芯片级快速验证方法——“基于C建模的SoC芯片级验证方法”。针对ARM处理器构建AMBA周期精确模型,总线设备周期精确模型可由Verilog RTL生成,快速进行周期精确的芯片级验证。以Garfield系列系统芯片1验证为平台。模块级验证过程中采用基于遗传算法和覆盖率驱动的验证向量自动生成算法生成验证向量,数据表明,相对手写和随机生成验证向量方法本方法能减少验证向量开发时间,并达到更高的覆盖率;采用域覆盖率衡量模块级验证工作的充分型,结果表明这种覆盖率相对于行覆盖率和路径覆盖率更能准确衡量验证工作的充分性和发现验证漏洞;模块级验证过程中采用C参考模型与SVA检查DUV(Design Under Verification)的响应是否和功能定义一致,结果表明该方法能减少调试时间,提高验证质量。模块验证达到所需要的域和功能覆盖率后,SoC验证重点转向芯片级(Chip-Level)验证,采用基于C建模的SoC芯片级验证方法验证整个芯片功能,数据结果表明该方法比传统的RTL仿真速度提高了20倍以上。更多还原

【Abstract】 Verification has been one of the most important challenges to SoC design. Despite recent advances in formal verification, it can not meet the requirement of design. Simulation based verification method continues to be the workhorse. This dissertation addresses the issues of simulation based verification.Firstly, proposed and implemented coverage driven and GA(Genetic Algorithm) based Verilog RTL verification vector auto generation algorithm. Coverage information is fed back and form a closed system, the GA analyses dynamically the coverage information and selects the vector with higher fitness to generate the next generation vector. Secondly, proposed and implemented Domain fault model, coverage metrics and testing points selecting strategies. Domain fault model correctly reflects the reason causing domain errors, Domain coverage metrics measure the quality of the verification approach, and test point selecting strategies generate required points for domain testing. Thirdly, implemented a C reference model and SVA(System Verilog Assertion) based function checking method. Lastly, proposed and implemented a C based SoC chip level verification method, in which a cycle accurate AMBA functional model is connected to ARM ISS and the devices on bus are translated from Verilog RTL.Preceding methods are used in Garfield series SoC2 verification approach. When doing block level verification, GA based Verilog RTL verification vector auto generation algorithm is used to generate the verification vector, results show that the algorithm can generate vector more quickly and reach higher coverage than directed and random method. Domain method is adopted to measure block level verification quality, domain coverage metrics can find more verification holes, compared with line and path coverage metrics. C reference model and SVA based checking method are also used in the block verification approach, results show that this method can reduce greatly verification time and human resource, locate the design error quickly. When block level verification reaches the required domain and functional coverage, the C based SoC chip level verification method is used to verification whole chip, results show that whole chip can be verified at speed of 20 times of Verilog RTL simulation.更多还原