【作者】 齐骥；

【导师】 龚育昌；

【作者基本信息】 中国科学技术大学 ， 计算机软件与理论， 2006， 博士

【摘要】 嵌入式系统在当今社会已无处不在，例如大家同常生活中用到的PDA、MP3、手机和在专门的场合应用的网络节点系统、医疗系统、穿戴电脑系统等，它一般由计算部件、外围设备、操作系统以及用户应用四个部分组成。可选的计算部件有专用集成电路ASIC(Application Specific Integrated Circuit)、指令集处理器ISP(Instruction Set Processor)和现场可编程门阵列FPGA(Field Programmable GateArray)。FPGA是一种可重构硬件，计算性能高且易于编程，非常适合同时具有高计算复杂度和多变工作集的应用。在嵌入式系统的复杂度、性能和上市时间等要求不断提高的今天，FPGA器件的应用范围正在变得越来越广泛。 随着半导体技术的发展，基于SRAM存储器件的FPGA容量已经达数百万门，且具有动态部分可重构功能，从而可随时加载、执行和删除独立的硬件逻辑模块。因此，FPGA已经成为一种可以动态分配的计算资源。由FPGA和ISP构成的可重构混成系统具有计算性能高、灵活性强、适用范围广等优点，目前已成为国际上研究的热点。 按照传统的设计观念，FPGA被视为硬件加速器，由用户直接管理和使用。而操作系统仅提供一些驱动作为支持。这种方式的设计难度很高，而且由于忽略了FPGA的可重构特性以及硬件逻辑模块间的潜在并行性，效率很低。为了提高FPGA的利用率、简化开发流程和提高系统的性能，操作系统必须对可重构器件提供更有效的支持。本文对可重构资源的管理和共享问题进行了深入的研究，提出了KVIT(Keeping the Vertexes Information of Tasks)布局算法、QFOAC(Quantifying Fragments by Occupied Area Concatenation)碎片量化方法和MGS(Minimum Gap Scheduling)调度算法。针对已有混成系统运行模型的缺陷，提出并设计了基于服务体／执行流模型SEFM(Servant & Exe-Flow Model)的，面向可重构混成体系结构的操作系统SEF-OSHRSfSEF Operating System for Hybrid Reconfigurable Systems)，实现了该操作系统的原型系统。 在OSHRS中，布局算法必须在保证布局质量的基础上，尽量减少布局开销。KVIT布局算法就是为解决这个问题而提出的。该算法尝试将新到达的硬件任务放置在已布局硬件任务的顶点处，并通过对可重构芯片内部计算单元进更多还原

【Abstract】 Embedded computer systems are omnipresent. They can be found in almost all parts of our infrastructure that are directly and consciously used by people day-to-day, or that are not consciously perceived by most of people. Examples of such systems are PDAs, Mp3 players, mobile phones, network nodes, medical treatment systems and wearable computers etc. Commonly, An Embedded System can be composed of computing units, I/O devices, an operating system and user applications etc. Optional computing unit could be ASIC, ISP or FPGA. FPGA is a kind of reconfigurable hardware with high performance and flexibility for programming, which is appropriate for applications combining high performance demands with frequent changes of their workloads. With the increasing request on complexity, performance and time-to-market of embedded computer systems, FPGA is becoming more and more popular.With the development of semiconductor technology, the capability of SRAM based FPGA has achieved several millions of gates. The partially reconfigurable FPGA can load, execute or delete individual hardware logic blocks at runtime which makes FPGA runtime allocable computing resource. The hybrid system composed of FPGA and ISP has the advantages of high performance, flexible programmability and more extensive usage, and it has become the focus of research in the recent years.On the traditional opinion of designers, FGPA acts as the accelerator of hardware that managed directly by the programmers, while the operating system afford no more support than some device drivers. This manner leads to a complicated design flow in the process of development. Furthermore, it is inefficient because of ignoring the potential parallelism of the individual logic blocks. The更多还原