【作者】 杨沛锋；

【导师】 谢孟贤；

【作者基本信息】 电子科技大学 ， 微电子学与固体电子学， 2002， 博士

【摘要】 移动通信、GPS、雷达及高速数据处理系统等的高速发展对半导体器件的性能，如截止频率、功耗和成本等提出了更高的要求。相对于Si器件和化合物半导体器件，Si／SiGe异质结器件能以更高的性能价格比满足该要求，故成为目前国内外研究的热点之一。本文通过对Si／SiGe异质结材料特性、生长技术、p-MOSFET、SiGe-HBT的研究，设计优化、试制出了SiGe-p-MOSFET和SiGe-HBT器件样品。 首先，通过理论分析和模拟，给出了Si／SiGe-p-MOSFET优化设计原则，主要包括：（1）栅材料的选择；（2）沟道层中Ge组分及其分布曲线的确定；（3）栅氧化层及Si盖帽层厚度的计量优化；（4）阈值电压的调节。应用以上原则设计了器件各参数，并制备了器件样品。测试结果显示，SiGe-p-MOSTET（L=2gm）跨导为45mS／mm（300K）和92mS／mm（77K），而作为对照的常规Si-p-MOSTET的跨导为33mS／mm（300K）和39mS／mm（77K）。 同时，提出了一种描述Si／SiGe-p-MOSFET中量子阱内空穴面密度的模型，其中考虑到了SiGe量子阱中最低的两个子价带，但暂未计及Si盖帽层中寄生沟道的影响。模型计算结果与MEDICI模拟结果的比较表明该模型可准确描述寄生沟道形成之前SiGe量子阱沟道中的空穴面密度。在大规模集成电路设计中该模型可用于模拟预测SiGe-p-MOSFET的阈值电压、电流-电压及电容-电压特性。 其次，详细分析了SiGe-HBT中基区不均匀掺杂、基区复合、异质结势垒效应等对器件性能的影响，设计、优化并试制出了器件样品。测试表明，器件的电流放大倍数为50，截至频率为5GHz。 在器件制备工艺方面，利用MBE，在450～550℃下生长了Si／SiGe合金薄膜，并得到了所需Ge组分的分布和掺杂（B和Sb）分布曲线，满足了器件制备的要求。 研究了应变Si／SiGe薄膜的工艺热稳定性，为确定热处理工艺条件，如热氧化、退火等的温度和时间，提供了实验依据。 700～800℃，30～150min湿氧热氧化Si盖帽层，得到厚度为15～20nm的SiO₂薄膜。在实验中发现，Si盖帽层的氧化速率要明显高于普通的Si材料，究其原因，主要是由于应力的存在、掺杂和Ge的外扩散有增强氧化的作用。 电子科技大学博士论文 利用PECVD，在300℃下采用低功率密度淀积生长了SIOZ薄膜，分别经700－850”C 60－305退火。退火后与退火前的界面态密度 Nss分另为 1．IX t’m－2·eVl和3118 X 101’cmZ．eV－‘ 在实验中提出并应用了实验版图的设计方法，其基本思路为将多张版图的内容经旋转一定角度后，集中排放在同一张版图上，在曝光时仍按一定角度旋转后再对准相应图形即可。该法以牺牲部分圆片有效面积为代价，大幅度减少实验流片中所使用的版图数量，节约了流片费用。 论文通过对SirsiGe异质结材料特性、生长技术、pMOSFET、SIGe卫BT的研究，设计优化、试制出了SIGe个－MOSFET和SIGe－HBT器件样品，能以更高的性能价格比满足移动通信、GPS及雷达等领域对高频、低功耗、低成本微电子器件的需求。更多还原

【Abstract】 The rapid development of mobile communication, GPS, radar and high speed date process system bring forward much higher demands to semiconductor device’s characteristics, such as cut off frequency, power dissipation, and cost. Compared with Si and compound semiconductor device, Si/SiGe heterojunction device can meet the demand with higher performance-cost ratio, so, which have become one of the hot fields in the world. In this paper, based on the research of Si/SiGe heterostructure characteristics, epitaxy technology and physical mechanisms of p-MOSFET and SiGe-HBT, SiGe-p-MOSFET and SiGe-HBT were optimized and fabricated successfully.Firstly, through theoretical analysis and computer aided simulation, optimized design principles for Si/SiGe-p-MOSFET are given, including the choice of gate materials, determination of Ge fraction and profile in SiGe channel, optimization of thickness of gate dioxide and silicon cap layer, and adjustment of threshold voltage. In light of them, SiGe-p-MOSFET sample was designed and fabricated. Measurement indicate that the SiGe-p-MOSFET’s (L=2|im) transconductance is 45mS/mm (300K) and 92mS/mm (77K), while in Si pMOSFET, it is 33mS/mm (300 K) and 39mS/mm (77K).At the same time, a simple model of the sheet hole density in 2DHG in Si/SiGe-p-MOSFET is presented. The presence of the first two sub-band energy levels in the quantum well are taken into account but the parasitic channel in Si cap layer is neglected for the time being. Comparison between data simulated by this model and MEDICI indicate that this model is accurate before the parasitic channel is formed. This model can be applied to simulate the threshold voltage, current-voltage and C-V characteristics of Si/SiGe-p-MOSFET in LSI simulation.Secondly, the influence of the base doping profile, base recombination and heteroj unction barrier effect (HBE) on the characteristics of SiGe-HBT were analyzed in detail. A device sample was designed and fabricated. The current gain is 50, and the cut off frequency is 5GHz.About the process, Si/SiGe alloy layers were formed by MBE at 450~550癈, which have proper Ge fraction and doping (B and Sb) profiles needed in device fabrication.IVThe thermal stability was researched in order to determine the process conditions, such as the temperature and time of thermal oxidation, anneal, and so on.Using wet thermal oxidation, a SiOi gate isolator is obtained at 700 ~800℃, 30~150min. The oxidation speed of Si cap layer is much more higher than that of conventional Si, which is mostly because the presence of strain, impurity and the out diffusion of Ge in SiGe channel.At the same time, the gate isolator is formed by PECVD, at 300℃ and a relative low deposition power is used. Before and after raped thermal anneal, the density of interface state is 3.118X 10ncm~2-eV"1 and 1.1 X 1011cm~2-eV~1 respectively.A new layout technique is given and used in our experiment. Through rounding, more than 3 pieces of layouts could be combined together, so that, the number of layout used in experiment could be reduced.更多还原