【作者】 张金灿；

【导师】 张玉明；

【作者基本信息】 西安电子科技大学 ， 集成电路系统设计， 2014， 博士

【摘要】 模数转换器（ADC）通过将采集的模拟信号转换成数字输出码连接了模拟量和数字处理系统，广泛应用于各类电子领域中。根据不同的应用领域对ADC系统指标的设计要求，已经出现了许多类型的ADC，其中，高速ADC越来越受到业界的关注。由于GaAs HBT器件具有混合微波单片集成电路所要求的高电阻衬底和高击穿电压的器件特性，因此本文采用GaAs HBT工艺实现模数转换器的设计。与CMOS相比，GaAs HBT具有潜在的更高的截止频率fT，并且由于GaAs HBT比InP HBT和SiGeBiCMOS的制作工艺更简单，因而GaAs HBT的流片成本也较适中。本文对GaAs HBT超高速折叠内插ADC芯片设计方法开展了研究。在对各类ADC结构进行分析的基础上确定了本文所采用的超高速ADC结构；提出了一种适用于GaAsHBT的考虑辐照效应的器件模型；并基于本文所建立的模型对ADC的电路级进行了设计。本文取得的主要研究成果如下：（1）研究了一款超高速ADC的设计与实现。该ADC的分辨率为6bits，采样率为3Gsps，基于WIN公司截止频率fT=60GHz的1μm砷化镓异质结双极型晶体管工艺设计。该ADC的设计采用折叠内插结构，以满足其Gsps级别的采样率，宽带宽和中等分辨率的要求，相比较于全并行结构，折叠内插结构降低了电路所消耗的功耗以及占用的芯片面积。（2）建立了ADC电路级设计所需要的GaAs HBT器件模型。为了预测GaAs HBT伽马辐照效应，建立了一种新颖的考虑了伽马辐照效应的GaAs HBT模型。首先，在对VBIC模型研究的基础上，根据GaAs HBT的特性，建立了一种简化VBIC模型；其次，从GaAs HBT辐照特性出发，对该简化的VBIC模型进行了进一步修正；最后，验证了模型的有效性。（3）本文所设计的超高速ADC包含有一个采样保持放大器，一个参考电阻串，四个折叠放大器，一个内插电阻串，一个比较器阵列，一个包含有异或门阵列、或非门阵列和15-to-4ROM的数字编码器，一个嵌有高低位同步电路的粗量化器，并且为了满足测试要求，片上还集成了对ADC输出数据流进行降速处理的1:4解复用器电路。（4）采用1μm InGaP/GaAs HBT工艺实现了6bits，3Gsps ADC的设计、流片和测试。ADC的芯片尺寸为4.32mm×3.66mm。采用高线性度的跟踪保持放大器提高了有效分辨率ENOB，并且在折叠放大器中采用额外的一次折叠系数消除折叠电路的边界效应改善了静态性能。测试结果表明，该ADC在3Gsps采样率的情况下，ENOB达到5.53bit，有效分辨率带宽为1.1GHz，微分非线性误差和积分非线性误差的最大值分别为0.36LSB和0.48LSB，在单电源6V电压供电下，所消耗的功耗为5.43W。与文献报道的高速ADC相比，本文所设计的ADC取得了较优良的有效带宽品质因子，在同类ADC设计中性能较好，处于国内先进水平。更多还原

【Abstract】 Analog-to-digital converters (ADCs) convert the analog signals (voltages, currents andetc.) into digital signals (normally binary), connecting the analog quantity to digital system,being widely used in various electronic field. There are many different types of ADCs usedfor quite distinct purposes. ADCs are designed according to their specifications. Among allkinds of ADCs, high-speed ADCs are becoming more and more important and widely appliednowadays.The gallium–arsenide (GaAs) heterojunction bipolar transistor (HBT) technology isadopted to implement the ADC system since many of its features are attractive, which areimportant in mixed-signal MMIC design, such as high resistivity substrate and highbreakdown voltage. In addition, GaAs HBT has potentially higher fTthan CMOS, and it isless costly than InP HBT and SiGe BiCMOS because of its simpler process.In this dissertation, the design approach of GaAs HBT ultra-high-speedfolding-interpolating ADC has been studied. Based on the analysis of various types of ADCstructures, ultra-high-speed ADC architecture used in this study was determined. A noveldevice model considering radiation effects for GaAs HBT was proposed. Based on the modelestablished in the dissertation, the ADC circuit was designed. The main studies andcontributions are as follows.(1) The design and experiment study of a high speed ADC, which is an essentialcomponent in communication systems, have been performed. The ADC features a6-bitresolution, a3-Gsps sampling rate and was implemented in WIN1μm GaAs HBT technologywith cutoff frequency fTof60GHz. Afolding-interpolating architecture was used in converterto provide the sampling rate of giga hertz, wide bandwidth and medium resolution as well asreduce the power dissipation and chip area of the circuit.(2) To complete ADC ciucuit-level design, a novel model for GaAs HBT was presentedin the dissertation. In order to predict the effects of gamma irradiation on GaAs HBT, a novelmodel was presented considering the irradiation effects. Firstly, according to thecharacteristics of GaAs HBT, a simplified VBIC model was proposed. Secondly, Based on theanalysis of irradiation-induced degradation in GaAs HBT, the simplified VBIC model wasfurther amended. Its validity was demonstrated by analysis of the experimental results ofGaAs HBT before and after gamma irradiation.(3) The ultra-high-speed ADC consists of a track-and-hold amplifier, a reference resistorladder, four folding amplifier, an interpolating resistor string, a comparator array, a digital encoder including an XOR array, a NOR array and a15-to-4ROM, and a coarse quantizerincluding a bit synchronization circuit. To meet the test requirements, a1:4DEMUX was alsodesigned on the chip.(4) The design and test results of a6-bit and3-Gsps analog-to-digital converter (ADC)using1μm GaAs HBT technology are presented in this work. The monolithicfolding-interpolating ADC makes use of a track-and-hold amplifier (THA) with a highlylinear input buffer to maintain high effective number of bits (ENOB) and1out-of-rangefolding factor of folding amplifier to improve the static performance. The ADC occupies anarea of4.32mm×3.66mm and achieves5.53bit ENOB with an effective resolutionbandwidth of1.1GHz at a sampling rate of3Gsps. The maximum DNL and INL are0.36LSB and0.48LSB, respectively. The ADC consumes5.43W from a single6V power supply.The presentedADC acheives5.08×1010the effective resolution bandwidth figure of merit.更多还原