【作者】 张岩；

【导师】 杨银堂；

【作者基本信息】 西安电子科技大学 ， 微电子学与固体电子学， 2013， 博士

【摘要】 随着集成电路进入纳米时代，芯片的特征尺寸不断减小而集成度持续上升，片上晶体管数目的增加大大提高了芯片的复杂度，连接芯片内部功能块的互连线结构也变的复杂，集成电路的设计重心由原来器件为主逐步向互连线上转移。集成电路的互连结构目前已经达到13层，加上低k低热导率介质材料的引入，导致互连线的热耗散路径变长、难度增大。互连线自身产生的焦耳热无疑升高了互连温度，而受温度影响的互连电阻的改变使得现有的互连线性能估算方法不再准确，这势必阻碍集成电路的发展。本文从自热效应的影响、互连线性能优化以及3D IC热管理角度开展研究，并取得了以下成果：(1)针对单根互连线，本文引进了可以减小互连线延时的非均匀互连线结构，验证了其在减小功耗方面也做出了一定的贡献。基于二端口电路的电流电压理论，推导出非均匀互连线输入、输出电流和电压，建立了包含前端驱动和后端负载在内的非均匀互连电路各部分能耗分布。在65nm工艺下，非均匀互连线的输出电压仿真结果同Hspice仿真结果比较非常吻合。针对互连线不同长度和不同负载电容值进行讨论，结果表明非均匀互连线的能耗分布模型比较适合长互连线和负载电容较大的互连电路。与均匀互连线相比较，非均匀互连线在功耗优化方面也起到了积极的作用。(2)基于分布式功耗模型，考虑自热效应，采用非均匀互连线结构建立了一种基于延时、带宽、面积、最小线宽和最小线间距约束的互连线动态优化模型。分别在90nm和65nm CMOS工艺节点下验证本文功耗优化模型的有效性,与同等条件的均匀互连线相比，在工艺约束下同时不牺牲延时、带宽、和面积所提模型能够降低高达35%的互连线功耗；分析结果表明该模型更适合负载电容小和驱动电阻大的互连电路；通过定性分析再次证明该模型互连线功耗优化的合理之处。该模型适用于片上网络构架中大型互连路由结构和时钟网络优化设计。(3)缓冲器插入的互连线一般都是较长的全局互连线，其位于离热沉较远的互连线结构顶层，散热较差，因此互连线自热效应严重影响到了全局互连线性能和电磁可靠性。传统缓冲器插入优化方法的建立都是基于互连线恒温状态，本文针对这一不足，利用互连线单位电阻与温度的线性关系，考虑互连线自热效应修正了电阻表达式。并通过作图的方式分析出自热效应对互连线延时、带宽、功耗和面积的影响。采用互连线各性能折中优化方法，引入性能品质因子这一概念，合理的建立了考虑自热效应后的插入缓冲器优化模型。针对90nm、65nm和40nm工艺节点进行仿真，仿真结果与不考虑自热效应情况相比，互连线线宽wopt、线间距sopt、缓冲器大小kopt和插入缓冲器的间距hopt的值都明显增大，并且考虑自热效应后互连线的延时、功耗和带宽能够获得更好的优化值。结果表明在实际生产中，由于不考虑自热效应，互连线性能优化所需结构尺寸明显偏小，导致互连工艺技术要求苛刻。(4)三维集成电路与二维集成电路相比，降低了全局互连和整个互连线长度，提高了互连延时、功耗方面的性能。特别是三维集成电路系统包含多个功能模块（数字模块、模拟模块、RF模块）和不同工艺技术(SOI, SiGe, GaAs等)，为集成电路的设计拓展了空间。在影响3D集成电路发展的诸多问题中，热管理无疑是最为重要的因素之一。基于Ankur Jain的三维集成电路一维热管理模型，本文提出了考虑横向热扩散效应的含硅通孔结构的三维热传输模型。仿真结果与ANSYS软件仿真结果比较具有很高的吻合度，针对变化的通孔密度、通孔直径、后端互连线层厚度和硅通孔填充材料，仿真比较了考虑通孔结构和不考虑通孔结构的叠层芯片各层温升，结果显示考虑通孔结构后的三维集成电路热扩散能力显著提高，证明了硅通孔结构在三维集成电路热扩散中的重要地位；对含有硅通孔结构的三维集成电路，同样比较了上述参数变化下考虑横向热扩散和不考虑横向热扩散的各层温升，结果表明，横向热扩散对于含硅通孔结构的三维集成电路热分析而言是不可忽视的。更多还原

【Abstract】 As the feature sizes of integrate circuits decrease to nanometer，the chip featuresize continues to decrease while integration level is improved continuously. Theincrease of the number of transistors enhances the complexity of chip. Theinterconnection, which connects function modules on chip, is becoming more complexas well. The centre of the design integrated circuit (IC) has shifted from electronicdevice to the interconnection. Variation of interconnect wire resistance, which resultsfrom the influence of temperature, and the adopting of new materials with low thermalconductivity lead to the deterioration of performance and reliability of the circuit. Thethermal problems of chip always restrict the development of IC. Consequently, theresearch of interconnection performance with consideration of the self-heating effect ofinterconnect is necessary.At present the number of metal layer has reached13in nanometer integratedcircuit, which result in a longer path between the interconnect wire and the substrateattached to heat sink for the heat dissipation of interconnection. In addition, adoption oflow dielectric constant materials in IC manufacture makes the interconnection heatmore difficult to dissipate. Interconnection Joule’s heat increases the interconnectiontemperature while seriously affects the accuracy of interconnection performanceestimation. The research centered on the effect of self-heating, interconnectionperformance optimization and thermal management of3D ICs. The main studies andconclusive results are as follows:(1) For single interconnect wire, a non-uniform interconnection structure whichcan low the interconnection delay effectively is introduced. Then the non-uniforminterconnection contribution on power reduction is proved. Based on the two-portnetwork current and voltage theory, the input and output current and voltage are derived.Last the energy consumptions distribution model of the interconnect circuit whichincludes front-end driver and back-end load. The proposed model is simulated at65nmCMOS technology. The concluded output voltage accords well with the simulationresult of HSPICE. Simulation results of the energy consumption are analyzed withdifferent interconnect wire length and different load capacitor. The energy consumptionsdistribution model is more applicable to long wire and large load capacitor forinterconnection. Compared with uniform interconnection, the adoption of non-uniforminterconnection structure works well on power optimization.(2) Based on the distributed interconnect power model, a novel dynamic power model is presented in this paper, which adopts a non-uniform interconnection structure.This model takes into account the self-heating effect and is constrained by delay,bandwidth, area, minimum interconnect width and minimum interconnect space. Thevalidity of the proposed model is verified at90nm and65nm CMOS technology. Theresults indicated that the proposed model can generate a power consumption reductionas high as35%, and yet the delay, area, bandwidth are not deteriorated, compared withthe conventional power model. The simulation results indicates that the proposed modelis more applicable to the interconnect circuit which has low load capacitance and largedriver resistance. The proposed optimal model can be used for design of large scaleinterconnect router and clock network in network-on-chip structure.(3) The interconnection which needed buffer insertion is a long global line. As it islocated far away from heat sink, the global interconnect has poor heat dissipationcapacity. Therefore, the self-heating effect greatly affects interconnect performance andelectromigration reliability. For traditional optimal buffer insertion, the model is basedon a constant temperature assumption. In order to resolve the shortage, the interconnectresistance per unit length is modification with the consideration of the sealf-heatingeffect since the interconnect resistance has a linear dependence on the temperature. Byusing the graphical mythologies, the relationships between sealf-heating effect and delay,bandwidth, power and area are analyzed. For the purpose of having a small delay, powerdissipation and area while having a large bandwidth, a general metric for the tradeoff onall of above performance is developed. The proposed optimal model is verified andcompared based on90nm,65nm and40nm CMOS technologies. It is found that thevalues of wopt, sopt, koptand hoptare larger than that of no considering the self-heatingeffect. More optimum results can be easily obtained by the proposed model. Thisoptimization model is more accurate and realistic than the conventional optimizationmodels, and can be integrated into the global interconnection design of nano-scaleintegrated circuits.(4) One of the most important benefits of three-dimensional (3D) architecture overa traditional two-dimensional (2-D) design is the reduction in global interconnects andtotal wire-length, thereby providing higher timing performance and lower powerconsumption. Further, a3-D integrated system can include multiple design disciplines(Digital, analog, RF) and disparate process technologies (SOI, SiGe, GaAs, etc.), thatextend the capabilities of the3D system, expanding the boundaries of the IC designspace. Of all the development-hampering factors for3D ICs, thermal management is undoubtedly the most important factors. Based on the one-dimensional heat transfermodel proposed by Ankur Jain, a3D analytical heat transfer model for3D ICs withthrough silicon via (TSV) is developed in this paper. The simulation results areconsistent with the result based on ANSYS. The results of analysis indicate thatincreasing insertion density of TSV, and radius of TSV, decreasing the thickness of backend of line and adopting TSV insertion of higher thermal conductivity can effectivelyimprove the heat dissipation of3D ICs circuits. It is proved that the importance of TSVin thermal diffusion for3D ICs. Meanwhile, The effects of the horizontal heat transferon the thermal management of3D ICs is analyzed when the number of strata, the TSVdensity, the TSV diameter and the thickness of the BEOL layer vary under the specificprocess and thermal parameters. The results indicated that the temperature rise,simulated by the model presented in this paper, is lower compared with the conditionwithout considering the horizontal heat transfer effect. The difference of the temperaturecan be above10%. And the effect of the horizontal heat transfer on the thermalmanagement of3D ICs is more obvious with the increase of integrated level. Since themodel presented in this paper conforms to the actual situation, it can be more accurate inanalyzing the temperatures of stacked chips in3D ICs.更多还原