【作者】 谢春蕾；

【导师】 严晓浪； 史峥；

【作者基本信息】 浙江大学 ， 电路与系统， 2014， 博士

【摘要】 在摩尔定律的驱动下,集成电路的晶体管密度每两年翻一倍,在保持生产成本不变的前提下,提高电路的性能,降低功耗。在过去的五十多年里,作为集成电路生产中的关键技术,光刻技术的发展成功将晶体管的尺寸从毫米级缩小到了纳米级。光刻光源波长的缩小一直是光刻技术发展的主要手段,然而,其缩小速度远小于集成电路特征尺寸的缩小速度。自从250nm工艺节点开始,光刻技术进入了亚波长光刻阶段——光刻光源的波长大于所要生产的图形的最小尺寸。分辨率增强技术也由此应用而生,以解决光刻过程中发生的图形畸变问题。光学邻近校正技术作为应用最为广泛,最为有效的分辨率增强技术之一,通过对光刻掩模板上图形的修改达到提高光刻保真度的目的。发展到目前,最先进的光刻技术在使用193nm波长的光源生产特征尺寸为22nm/17nm的芯片。生产图形的尺寸只有光源波长的十分之一左右,光刻技术发展进入了一个新的阶段——深亚波长光刻阶段。相应的,深亚波长光刻技术对光学邻近校正也提出了新的挑战和要求——新的设计类型和更高的图形密度,更高的校正效率和校正精度。本文分别针对光学邻近校正中光刻仿真、图形切割和层次结构处理三个步骤提出了新的解决方法,以满足深亚波长光刻的需要。这些新方法被应用于自有的光学邻近校正软件ZOPC中,并成功处理了多个工业界产品。本文的主要内容和创新点概括如下：针对一维版图的快速光刻仿真。在现代集成电路生产过程中,快速平面光刻仿真对集成电路版图优化和光刻系统优化都具有至关重要的意义。随着集成电路生产工艺进入“深亚波长光刻”阶段,一维版图设计规则被广泛研究和采用。本文充分利用光刻系统中光源的部分相干特性和一维图形的特性,提出了针对一维版图的快速平面光刻仿真算法。该方法由一维基元图形查表法、最小查找表及其边缘延伸和无切割的大面积版图仿真组成。仿真结果表明,在保证极高准确性的基础上,相比于传统的快速仿真方法,该方法将查找表的建立时间缩短了95%以上、基本图形的仿真速度提高了48%左右、大面积版图的仿真速度提高了70%以上。面向集成电路功能性和成品率的图形切割方法。随着集成电路特征尺寸的不断缩小,集成电路生产过程中掩模数据量的不断增长,极大的增加了生产成本。应用于掩模版图的光学邻近校正增加了版图的复杂度,是成本增长的原因之一。本文提出了一种全新的切分方式,基于对版图中影响成品率的图形的识别,该切分方法可以在保证关键部位的校正质量的同时,简化校正后版图的复杂度,减少最终掩模版图的数据量。实验结果显示使用该切分方法得到的掩模版图数据量大小只有通过传统方法得到的一半左右,校正时间也减少到了传统方式的四分之一左右。针对阵列式版图和随机逻辑电路版图采用不同策略的混合式层次结构处理方法。随着集成电路技术的不断发展,一套集成电路版图中所含有的图形数量在急速增加,数据量也相应的飞速增长。传统的集成电路设计工具往往将设计版图按照一定的层次结构来储存,通过数据的重用来提高存取速度和处理效率。本文提出了针对阵列式版图和随机逻辑电路中不同的版图特点,采用不同策略的混合式层次结构处理方法。该方法在保证校正精度的前提下,最大限度的减少校正过程中的冗余运算,提高校正效率,降低校正时间,并有效减少了校正后版图的数据量。实验结果显示,与传统的扁平式校正方法相比,混合式层次处理方法可以将校正时间和校正后版图数据量分别减少80%和90%以上。实验和流片结果则双双验证了该方法的准确性。更多还原

【Abstract】 Being driven by Moore’s law, the transistor density of integrated circuit doubles every two years, while the performance of the circuit increases, the power consumption of the circuit decreases, and the production cost remains the same.In the past fifty years, as the key technique of IC manufacturing, the development of lithography has successfully enabled the shrinking of transistor’s size from millimeters to nanometers. The development of lithography mainly relies on new light sources with shorter wavelength. But the shrinking speed of the wavelength is much slower than that of transistor’s size.Since the250nm technology node, wavelength of light source has been greater than the feature size of the pattern to be produced, which is called as sub-wavelength lithography. Hence, resolution enhancement technologies (RETs) are developed to reduce the pattern distortion in lithography. As the most widely used and most efficient RETs, optical proximity correction (OPC) improves the fidelity of lithography by modifying the layout patterns on the lithography masks. Nowadays, the most advanced lithography technology produces IC chips with22nm/17nm feature size using193nm wavelength source. The size of produced pattern is only about tenth of the source’s wavelength, which means the lithography technology has moved into one new stage, namely the deep sub-wavelength lithography. Accordingly, deep sub-wavelength lithography has created new requirements and challenges for OPC technology. The new design style is developed; the pattern density is getting higher; and the correction is demanded to be more efficient and accurate. This dissertation proposes some new solutions for lithography simulation, dissection and hierarchy process, which are the three main steps in OPC, to fulfill the demands of deep sub-wavelength lithography. These innovations have been implemented into the proprietary ZOPC software, which has successfully processed a couple of industrial products. The main contents and innovations are summarized as follows: A fast lithography simulation method for1-D layoutIn modern IC manufacturing process, fast lithography simulation becomes one of the most significant technologies for IC layout optimization and optical system optimization. Meanwhile,1-D layout design rules are intensively studied and widely used to get better printability, as IC technology scales down to process node with "deep sub-wavelength lithography". In this dissertation, one fast lithography simulation methodology is proposed for1-D layout, taking advantage from the characteristics of partial coherent system and1-D pattern. The new methodology consists of look-up table based on1-D basis pattern, the minimum look-up table and its boundary extension, and simulation of large scale layout without division. Simulation and experiment results show that the building time of look-up table is reduced more than95%, the simulation speed for basic pattern improves about48%, and the simulation speed for large scale layout improves more than70%with highly accuracy, when the new algorithm is compared with conventional method.A novel dissection method based on circuit functionality and yieldAs the feature size of IC shrinking smaller, growing data volume of mask tremendously increases manufacture cost. The cost increase is partially due to the complicated Optical Proximity Corrections (OPC) applied on mask design. In this dissertation, a yield-aware dissection method is presented. Based on recognition of yield related mask context, the dissection result provides sufficient degrees of freedom to keep fidelity on critical sites while still retaining the frugality of modified designs.Experiments show that the final mask volume using the new method is reduced to about half of that of conventional method, and the runtime of OPC is reduced to about a quarter of the conventional method.Hybrid hierarchical processingWith the development of IC technology, the number of patterns in one set of design layout increases rapidly, which also increases the data volume of the design layout. Normally, IC design tools organize the design layout in a certain hierarchical structure, by which the access speed and process efficiency is improved, because of the data reusing. According to the different characteristics of array layout and random logic layout, this dissertation presents a hybrid hierarchy processing method to handle these two kinds of layout with different strategies.With guarantee of high correction accuracy, the new method removes the redundant correction as much as possible. As a result, the correction efficiency is improved, and the data volume of the corrected layout is reduced. The experiments show that the hybrid hierarchical processing reduces the runtime for full-chip correction by80%and the data volume of corrected layout by90%, while being compared with the conventional flatten approach. Both experiments and tape-out results verified the accuracy of this method.更多还原