【作者】 史妮妮；

【导师】 孙永节；

【作者基本信息】 国防科学技术大学 ， 软件工程， 2010， 硕士

【摘要】 在高速串行RapidIO数据通信中,作为一种基于可靠性的开放式互连协议标准,RapidIO以其高效率、高稳定性、低系统成本的特点,为通信系统各器件间提供了高带宽、低延时数据传输的解决方案。由于时钟抖动、偏斜、队列间同步以及串扰噪声等各种非理想因素的影响,同时考虑到硬件开销,一般只传送数据信号而不传送与数据信号同步的时钟信号。为了保证接受端的数据同步问题,采用了时钟数据恢复电路(CDR)技术。本文在对RapidIO互联规范理解的基础上,根据RapidIO互连规范对CDR的性能要求,在0.13um CMOS工艺下设计实现了面向RapidIO应用的CDR关键电路。本文的主要工作以及创新之处包括以下几方面:1.通过对CDR的几种实现结构的研究和比较,以及考虑到设计中的速度、抖动性和稳定性的最大设计限度,本文采用了基于锁相环结构的CDR,结合相位选择插值技术和多重相位技术来实现时钟数据的恢复。2.考虑到环路的稳定性和速度,对鉴相器和电荷泵进行了设计改进,使鉴相器的死区和一般电荷泵的非理想特性得到很好解决,并通过Hspice模拟验证。3.对多相时钟产生机制的深入研究,设计了基于单端环形结构的振荡器,将3级结构和5级结构的VCO进行环路嵌套,实现八相等相位差的时钟信号,相邻两相相位差为π/4。4.遵循高速数模混合电路版图设计准则,完成了CDR核心模块的版图实现。电路的模拟结果显示该设计实现的CDR满足了串行RapidIO互连规范的传输要求。更多还原

【Abstract】 In the high-speed serial RapidIO data communication, as an opening interconnect protocol standards which based on reliability, RapidIO features in its high efficiency, excellent stability and low system cost, which provides a smart data transmission solution with high-bandwidth and low-latency for the communication between devices in systems. Considering the various non-ideal factors including the clock jitter, skew, queue synchronization and crosstalk noise, and along with the hardware cost, it generally transmits data signals instead of clock signals which synchronized with the data signal. In order to ensure the data synchronization problems of the receiver, we employ the clock and date recovery circuit (CDR) technology.The paper based on the interpretation of RapidIo interconnect architecture, with regard to the performance requirements of CDR, successfully explored critical circuit of CDR with the 0.13um CMOS technology, which is mainly applied to the high-speed serial RapidIO.The major contents and highlights of the research are as follows:(1) Through the study and comparison of several different kinds of CDR, and with consideration of the maximum design limits of speed, jitter and stability , The paper employ a CDR which based on PLL structure , combined with phase select interpolation technology and multi-phase technology to realize the clock signal recovery.(2) Taking stability and speed into account, we bettered the design of charge pump and voltage controlled oscillator, thereby the dead-region of FD and the non-ideal characteristics of common charge pump would get a preferable solution, and get through the Hspice simulate verification.(3) With in-depth research on the multiphase clock generation mechanism, design an oscillator which based on single-ended ring structure, nesting the VCO which has the three-grade structure and five-grade structure into loop structure, so as to achieve a clock signal with eight-phase equal phase difference ,whose adjacent phase difference isπ/4.(4) obey the high-speed digital hybrid circuit layout guidelines, realizing the layout design of the core CDR modules. The simulation results of circuit well satisfy the demands of the serial RapidIo interconnect architecture transmission requirements.更多还原