【作者】 李艳花；

【导师】 李永绣；

【作者基本信息】 南昌大学 ， 应用化学， 2010， 硕士

【摘要】 化学机械抛光(CMP)作为超大规模集成电路制造(ULSI)工艺中公认的最佳平坦化加工工艺,已成为ULSI制造中不可或缺的技术。为满足ULSI对高精度超光滑表面的要求,需要发展新的CMP技术及其相关的材料。目前,硅片抛光采用的是SiO2胶体粒子,而铈基氧化物作为硅片抛光的研究报道比较少。本文分别合成了纳米CeO2以及钛均匀掺杂和钛包覆CeO2粒子,研究了它们抛光硅片的工艺条件和抛光性能,探讨了硅片抛光性能提高的原因。以硝酸铈为原料,十二烷基苯磺酸钠为分散剂,过氧化氢为氧化剂,氨水为沉淀剂,采用直接沉淀法制备了粒径分布均匀的纳米氧化铈粉体,并通过XRD、TEM等手段对粉体进行了表征。采用所制备的氧化铈粉体配置成抛光浆料对硅片进行抛光,研究了浆料pH值、固含量及过氧化氢浓度对n型半导体硅晶片(111)晶面抛光性能的影响。确定了最佳的抛光条件为：pH值10.5,含固量为0.5%,过氧化氢体积分数为1.5%,此时的抛光速率为61.1nm/min,所抛光的硅晶片的表面粗糙度为0.148 nm。以CeO2纳米粉体为核晶,Ti(SO4)2为钛源,CTAB为表面活性剂,采用胶体水解法制备了TiO2包覆CeO2核壳复合粉体,并优化了合成条件以及抛光工艺。结果表明：包覆TiO2可以提高抛光速率,且与包覆量有关。当TiO2的包覆量为CeO2质量的10%时(合成时加入了1.1ml抑制剂,在800℃煅烧2h),合成的TiO2@CeO2核壳纳米复合粉体的抛光效果最好。在加入1.5%H2O2时测定的MRR达到了65.4nm/min,所抛硅片的表面粗糙度Ra为0.144nm。与掺杂10%TiO2后粉体的抛光速率相比,包覆10%TiO2得到的TiO2@CeO2粉体的抛光速率要低一些。更多还原

【Abstract】 As the best technique for the planarization processing of ultra large scale integration circuits (ULSI), chemical mechanical polishing (CMP) has became an indispensable technique in the manufacture of various devices with ultra-smooth surface. In order to meet the demand of next generation ULSI, it is necessary to develop new CMP techniques and the relating materials. SiO2 gel particles are currently employed in silicon wafers polishing. It is suggested that ceria or ceria based composites show great performance for replacing silica as abrasive particles in polishing slurries for silicon. In this study, nanoparticles of CeO2, Ti doping Ceria and Ti coating Ceria were prepared and their performance for polishing silicon wafer were comparatively examined with respective to their physical and chemical characteristics.Firstly, Ceria nanoparticles were prepared by direct precipitation using cerium nitrate as raw material, sodium dodecyl benzene sulfonate as dispersion agent, hydrogen peroxide as oxidizing agent, and ammonium hydroxide as precipitant. XRD、TEM and so on were used to characterize Ceria.The effects of process parameters, including slurry pH, ceria content, and hydrogen peroxide concentration, on the material removal rate (MRR) in the CMP of n-type Si(111) were investigated. A maximum MRR value of 61.1nm/min was obtained using 0.5%(w/v) ceria slurry with 1.5%(v/v) hydrogen peroxide and adjusting pH 10.5, in flow rate 2000 ml/min, rotational speed 128 r/min, pressure of 6.60MPa.Correspondingly, the surface roughness Ra of polished n-type Si (111) wafer is 0.148nm.Secondly, TiO2@CeO2 core-shell composite powders were prepared by gel hydrolysis precipitation method using CeO2 as crystal seeds, Ti (SO4) 2 as raw material of Ti, CTAB as surfactant. The optimum synthesis conditions and polishing techonology were determined. The MRR value of polishing silicon using slurry containing TiO2@CeO2 core-shell composite powder coated with 10% TiO2 (synthesized under the existing of inhibitor and calcinations temperature at 800℃for 2h) and 1.5%(v/v) hydrogen peroxide was determined to be 65.4 nm/min, which is lower than that polished with ceria doped with 10% TiO2. Correspondingly, the surface roughness Ra of polished n-type Si (111) wafer is 0.144nm, which is less than that polished using pure CeO2.更多还原