节点文献
基于高速LVDS的串并转换电路设计与研究
【作者】 李伟伟；
【导师】 廖家轩；
【作者基本信息】 电子科技大学 ， 微电子学与固体电子学， 2010， 硕士
【摘要】 随着信息技术的发展,数据量越来越大,传统的I/O接口由于自身的限制越来越不能满足现实需求。低压差分信号传输技术(Low Voltage Differential Signaling,LVDS)具有低噪声、低功耗、高可靠、节省成本和强集成能力等优点,因此成为了解决I/O接口问题的一种新技术。本文基于ANSI/TIA/EIA-644标准,研究了基于高速LVDS的串并转换电路。在此基础上,根据功能将其分为LVDS接收电路和串并转换电路两个主要模块。在LVDS接收电路中,通过ESD保护电路、轨对轨放大电路、迟滞比较电路、整形缓冲电路和失效保护电路的设计,完成了将2.5Gbps的LVDS信号转化为CMOS信号的工作。仿真结果表明,整个LVDS接收电路的延时为0.45ns,上升时间为0.04ns,下降时间为0.03ns,占空比为37:36,满足设计要求。在串并转换电路中,为了满足高速和低时钟的要求,采用一种树型结构和移位寄存器结构级联的串并转换电路。通过占空比为1:4的5分频器、树型结构串并转换电路和移位寄存器结构串并转换电路的设计,将1路2.5Gbps的数据转化为10路250Mbps的数据。仿真结果表明,整个串并转换电路的功能正确,满足设计要求。此外,本文在版图方面进行了研究,对匹配、串扰、噪声、寄生效应、闩锁效应和天线效应分别进行了论述,给出相应的解决办法。并基于1P8M 0.13μm CMOS工艺,采用全定制完成了版图设计。LVDS接收电路版图面积为74×96 ? m2,满足I/O标准;串并转换电路版图面积为80×83 ? m2。后仿真结果表明,本文设计的串并转换电路满足要求。
【Abstract】 With the development of information technology, the amount of data transmission is more and more increasing. Due to its limitations, the traditional I/O interfaces can not meet people’s needs. Low Voltage Differential Signal Transmission Technology has low noise, low power, high reliability, saving cost and strong integration capability. So it becomes a new technology to the solution of I/O interface.This paper which studies the deserializer based on high speed LVDS is under ANSI/TIA/EIA-644. On this basis, according to the function, it can be parted two main modules—the receive circuit of the LVDS and deserializer.In LVDS receiver circuit, the ESD protection circuit, rail to rail amplifier, comparator circuit, shaping-buffer circuits and fail-safe circuits transform 2.5Gbps of LVDS signals into CMOS signals. Through Simulation, the LVDS receiver circuit delay 0.45ns. The rise time is 0.04ns, and the fall time is 0.03ns ,Duty cycle is 37:36. It meets the design requirements.In deserializer, in order to meet the requirements of high speed and low clock requirements, it is wonderful to use a tree structure deserializer and register structure deserializers. Through the duty cycle of 1:4 divider(divide-by-5), tree structure deserializer and register structure deserializer, it completed down to a 2.5Gbps data into the data of 10 road 250Mbps. Through simulation, it has the correct function and it is enough to meet the design requirements.Besides, layout is researched in-depth. Discussing the matching, crosstalk, noise, parasitic effects, the latch and antenna effect, I give appropriate solutions. The design based on 1P8M 0.13μm CMOS process is completed using full-custom layout method. Layout of the LVDS receiver circuit is 74×96 ? m2 and it meets the standard of I/O. Layout of the deserializer is 80×83 ? m2. Post-simulation shows that the deserializer meets the design requirements.