【作者】 胡春；

【导师】 应建华；

【作者基本信息】 华中科技大学 ， 软件工程， 2009， 硕士

【摘要】 本文设计的是12位逐次逼近型ADC(Analog to Digital Converter)，主要包括采样/保持电路、比较器、DAC(Digital to Analog Converter)模块以及带隙基准电流源。采样/保持电路采用的是CMOS开关，比单沟道MOS开关有更大的导通状态动态范围。其中的单位增益运放采用的是rail-to-rail差分输入结构，实现了输入共模范围从0到Vdd的轨到轨输入，电流补偿技术使得输入跨导恒定，从而减小了频率补偿的难度使得相位裕度达到了78°，Class AB的输出方式使得运放在保持高效率输出的情况下减小了信号失真，同时折叠式共源共栅负载和两级放大的结构使运放能够达到90dB的高增益。比较器的输入和负载部分同运放一样，不同的是输出采用的是推挽输出，该结构能够保证在不牺牲速度的情况下，提高其驱动大容性负载的能力。DAC模块采用的是串行电阻电压按比例缩放结构，由相同类型DAC缩放组合分别处理高、低六位有效字，使得该模块的面积尺寸缩小很多。带隙基准电流源的基准电压随温度变化的幅度很小，温度曲线表明三种模型下总的温度系数为46.67 ppm/℃。整个电路的仿真采用的是0.25 CMOS工艺，电源电压为3.3Vμm。仿真软件采用的是Synopsys公司的Hspice-2005。仿真结果表明，设计的ADC分辨率在允许的共模范围中间电平能够达到12位，功耗为6.6mW，积分非线性INL和微分非线性DNL均超过了1LSB，在性能方面需要提高。更多还原

【Abstract】 This paper presents the design of a 12bit successive approximation (SAR) ADCmainly including sample/hold circuit, comparator, digital logic control, DAC module andbandgap reference current circuit. The sample/hold circuit adopted CMOS switches toincrease its dynamic area comparing with single channel switch in induced condition. Theunity-gain amplifier in the sample/hold circuit adopted rail-to-rail differential inputarchitecture to improve the common input range from 0 to Vdd to realize full scaleinput.Current compensation ensured input transconductance gm constant to easyfrequency compensation making the phase margin reach 78°.Its Class AB output wayweakened the signal distortion with high output efficiency. Besides, two level amplifieringstage and folded cascode architecture maintained high gain to reach 90dB.As for thecomparator, input and load parts are the same with the unity-gain amplifier. The differencebetween them was that comparator adopted push pull output way to improve its ability ofdriving large capacitance load. DAC module adopted voltage scaling architecture of seriesconnecting resistors to process high six MSB and low six LSB respectively, which larglydecrease the module size.Temperature coefficient of bandgap reached 46.67 ppm/℃.The whole circuit system was simulated on 0.25μm CMOS process, power supply is3.3V. The simulating software was Synopsys Company’s Hspice-2005. The simulationresult shows that the designing ADC sensitivity is 12bits, power consumption is 6.6mW,INL and DNL exceeds 1LSB which indicates the performance needs to be improved.更多还原