【作者】 佘振东；

【导师】 刘政林；

【作者基本信息】 华中科技大学 ， 软件工程， 2009， 硕士

【摘要】 卷积码是一种在数字移动通信系统中应用极为广泛的信道纠错编码。维特比(Viterbi)译码算法是最常用的卷积码译码算法。而维特比译码器的计算量、存储容量及功耗,会随其关键参数约束长度K的值成指数增长。这个特点使得大K值的维特比译码器在数字通信系统中,特别是移动设备、环保设备、手持设备等场合的应用受到很大限制。功耗问题己成为制约维特比译码器进一步发展与应用的瓶颈。本文对维特比译码器进行低功耗研究,并设计实现了基于现场可编程门阵列(FPGA)的大约束长度(K=9)维特比译码器,对降低数字通信系统电能消耗、改善散热性能、延长手持设备的待机时间具有重要积极的实用意义。本文采取自上而下(Top-Down)的设计方法。首先对维特比算法及其低功耗设计技术进行简要分析和总结,再根据维特比译码算法流程进行功能模块划分,并从实际应用的角度出发,根据大约数长度维特比译码器的结构特点,对各功能子模块进行低功耗优化设计,最后将其集成为维特比译码器系统。本文使用Verilog硬件描述语言进行电路设计,选用Altera公司全铜互连130nm工艺Cyclone系列FPGA,在QuartusII开发平台完成整个系统的性能验证及功耗分析,并与相关文献及Altera提供的维特比译码器MegaCore作对比分析。对比功耗分析结果表明,本设计可在保证译码器正常应用功能和纠错性能的前提下,使FPGA总功耗得以大幅度降低。更多还原

【Abstract】 Convolution code is a widely used channel FEC in digital mobile communication system. Viterbi algorithm is a common way for the Convolution code decoding process. Meanwhile, the power and resources consumption is increased significantly with the rise of key parameter: constrain value k. This feather result the conditionality use of Viterbi algorithm which based on large constrain value, especially as mobile phone and some other equipment that need batteries. Power consumption has been the main problem of the Viterbi decoder. This paper studied the technology of low-power consumption in Viterbi decoder, and has finished this design whit FPGA. It is useful to decrease the power consumption for the digital communication system.This paper uses a top-down design flow. First analyzes the Viterbi design flow, separate the whole decoder into several functional module. Then design the functional module into low-power consumption module according to the actually demand. At last put them together to integrate the whole Viterbi decoder system. Verilog HDL is used in this design as hardware describe language. This paper choice a 130 nm Cyclone to perform the whole design separately and QuartusII platform is used to synthesis and verification. Meanwhile some papers and a Viterbi decoder MegaCore as a reference are applied to do a power comparison. The result shows that power consumption of current design can decrease greatly while offering a necessary performance and speed.更多还原