【作者】 陈娟娟；

【导师】 徐静平；

【作者基本信息】 华中科技大学 ， 微电子学与固体电子学， 2009， 硕士

【摘要】 随着集成电路技术的发展,晶体管的特征尺寸已经减小到45nm以下,栅氧化层的物理厚度小于2nm,导致栅极漏电流增大,采用高k材料取代二氧化硅是一种抑制栅极漏电流增大的有效手段。但是,高k材料作为栅介质时,会导致器件沟道迁移率的退化。因此,高沟道迁移率材料锗成为最有可能替代硅的MOS器件沟道材料之一。目前,高k栅介质/ Ge-MOS器件结构、制备工艺和电特性已经成为学术界和工业界的研究热点。本文采用业界广泛使用的Synopsys公司模拟软件MEDICI对高k栅介质Ge-MOSFET的电特性进行了研究。通过考虑短沟道效应,着重分析了栅介质介电常数、氧化物固定电荷密度以及沟道长度等对器件阈值电压和亚阈斜率的影响,通过对阈值电压(Vth)、亚阈值斜率(S)等进行分析,确定出适用于薄栅Ge-MOSFET的最佳k值,为以后的器件设计提供理论指导。同时,通过求解高k栅介质耗尽区与栅绝缘层区域的泊松方程,得到叠层高k栅介质阈值电压模型。该模型考虑了界面层对Vth的影响,仿真结果表明界面层有利于改善器件的阈值特性。实验方面,采用高真空电子束蒸发技术,在Ge衬底上淀积La2O3高k介质薄膜制备了La2O3介质/ Ge-MOS电容。通过不同衬底温度时栅介质薄膜淀积工艺研究,确定出合适的衬底温度。研究了O2、NO、NH3和N2不同气体退火对MOS电容电特性的影响,发现La2O3在N2气氛中退火后由于形成稳定的LaGeOx界面层而有效地降低了Qox和Dit,同时获得较高的栅介质介电常数。采用磁控溅射技术,在Ge衬底上分别淀积了La2O3和LaON介质层薄膜,制备了La2O3和LaON介质/ Ge-MOS电容。电特性研究表明,与La2O3 /介质Ge-MOS相比,LaON介质/ Ge-MOS有更低的界面态密度、低的氧化层电荷密度和低的栅极漏电流。而且,LaON介质层更高的等效k值,有利于减小等效氧化物厚度(EOT)。通过对电子束蒸发和磁控溅射制备的La2O3 / Ge-MOS电容电特性的研究,发现磁控溅射方法制备的器件有更好的界面特性和栅极漏电特性。更多还原

【Abstract】 With the aggressive reduction of characteristic length of MOSFET and the continuous improvement of integrated circuits, the characteristic length of transistor has been reduced to less than 45nm. And the physical thickness of gate is less than 2nm. It leads to a larger gate leakage current. Consequently, it is necessary to replace the conventional gate insulator, SiO2, with a high-k material for low power consumption. As application of the high-k materials as gate dielectric, problem of mobility degeneration occurs. It’s necessary to use high mobility channel material Ge to replace Si. At present, the device structure, fabrication process and electrical characteristics of high k / Ge-MOS device have already become the research focus of industry and academe.A series of electrical characteristics of Ge-MOSFET are analyzed and researched with the MEDICI simulation software of the Synopsys Corporation, which is widely used in industry. Short channel length effect is considered. Impacting on the threshold and the sub-threshold slope of device by the permittivity of gate dielectric, the fixed charge of oxide and the channel length is analysed. The optimal k value is chosen by analysing the threshold and the sub-threshold slope. It can be therory guidance for the following device design. By solving the Poisson equation of the depletion region of high k gate dielectric and gate insulator region, the threshold voltage model of stack high k gate dielectric is got. Effect of interlayer on the threshold voltage has been considered in this model. Simulation results indicate that low k interlayer is in favor of improving the threshold voltage of device.Ge-MOS capacitors with La2O3 as gate dielectric are fabricated by E-beam evaporation of La2O3. At first, the influces of different film deposition base temperature on electrical characteristics of Ge-MOS capacitor is investigated. Thus proper base temperature of film deposition is decided. Then effections on characteristics of MOS capacitor by post-deposition annealing in different gases (O2, NO, NH3 and N2) are studied. Experimental results indicate that the sample annealed in N2 exhibits not only larger k value, but also lower Qox and smaller Dit for the formation of LaGeOx interlayer in the annealling in N2.Finally, Ge-MOS capacitors with La2O3 and LaON as gate dielectric are fabricated by magnetron sputtering. By investigating the electrical characteristics of the LaON / Ge-MOS and the La2O3 / Ge-MOS, it can be seen that LaON / Ge-MOS has better electrical characteristics: lower interface-state, lower oxide-charge densities, and lower gate leakage. Moreover, LaON / Ge-MOS has higher dielectric constant and is fit for reducing capacitance equivalent thickness (EOT). Then the electrical characteristics of Ge-MOS capacitor with E-beam evaporation and magnetron sputtering are investigated. Experimental results show that the MOS devices fabricated by magnetron sputtering have better interface and gate leakage current properties.更多还原