【作者】 李荣春；

【导师】 窦勇；

【作者基本信息】 国防科学技术大学 ， 计算机科学与技术， 2009， 硕士

【摘要】 信道译码是软件无线电的关键环节,主要用差错控制的方法来纠正经过信道传输后所接收的码元错误。信道译码通过纠错码技术来实现。所谓纠错码技术,就是一种通过增加校验信息来提高信息传输可靠性的有效方法。常用的纠错码主要有卷积码、Turbo码、RS码和LDPC码四种。在不同的通信系统中,纠错码种类的不同;而同一类型的纠错码在不同的通信系统中参数标准也不尽相同。现代通信越来越倾向于实现各种不同标准的通信系统间的通信,传统的ASIC系统已经很难适应多变的需求。为了提高兼容性,译码器必须实现参数化可配置计算。基于FPGA的译码器模板便应运而生。本文针对纠错码中的卷积码、Turbo码、RS码和LDPC码这四种纠错码,分析了其译码原理及参数类型,设计每类纠错码的译码器模板,根据参数的变化自适应选择相应的体系结构,实现了不同通信系统中纠错码的参数化可配置译码,有效地实现了译码器的兼容性,以适应通信中的不同应用环境。本文还对四类纠错码可重构译码器构建技术进行了研究,设计了动态可重构纠错码译码器原型系统,对可重构译码器的存储结构、配置字控制技术进行了研究,并将四种纠错码的译码器在原型系统中进行了映射实现。更多还原

【Abstract】 Channel decoder is the vital link of the SDR (Software Defined Radio). The purpose of channel decoder is to correct the error of the received codes travelling through channel by means of the error control method. Channel docoder is implemented by error correction coding, an effective method to enhance the thransmission authenticity by adding the parity bits into the code. There are four popular FEC (Forward Error Correction Codes): convolution code, Turbo, RS and LDPC. The type of the FEC varies in different communication systems and the parameters of the same type FEC also vary in different communication systems. Unfortunately, it is a tendency to communicate between several systems with different standards in modern communication. Tranditional ASIC can not meet the changeful requirement of the new comminication systems. So the docoder should support configurable parametric computation to elevate its compatibility. The template docoder on FPGA is designed to slove the problem.Four FEC were studied in this paper: convolution code, Turbo, RS and LDPC. The decode principle and the parameters of each type of FEC were analysed firstly in this paper. The designed decoder template of each type of FEC can alter its architecture based on different parameters. The decoder template was designed to support configurable parametric decode process to realize the portability and compatibility to adjust the varied environment of communication.The study to FEC prototype decoder building was also made in this paper. The structure of dynamic reconfigurable system was designed. The design of configurable storage and the control technology of configurable instructions were studied and implement in the prototype. Each type of FEC docoder can be implemented in this prototype perfectly.更多还原