【作者】 祝媛；

【导师】 胡辽林；

【作者基本信息】 西安理工大学 ， 光学工程， 2010， 硕士

【摘要】 数字复接就是依据时分复用原理完成数码合并的一种技术。在数字通信网中,数字复接不仅仅是与信源编码、数字传输、数字交换相并列的专门技术,而且还是网同步中的帧调整、线路集中器中的线路复用及数字交换中的时分接续等技术的基础。近年来,随着用户需求的变化和传输技术的发展,光通信领域的准同步数字系列(Plesiochronous Digital Hierarchy,简称PDH)正逐渐被同步数字系列(Synchronous Digital Hierarchy,简称SDH)所取代,但是PDH因其容量适中,配置灵活,成本低廉和功能齐全,可针对客户不同需要设计不同的方案,在某些特定的接入场合(例如对传输容量需求不大)仍具有一定优势。论文对准同步数字复接和分接关键技术进行了深入的研究,根据现实需要,设计了一个四路E1(欧洲的30路脉冲编码调制,或称基群,速率2.048Mbps)／E2(二次群,速率8.448Mbps)准同步数字复接系统的FPGA方案,其主要功能可由单片FPGA实现,该解决方案在集成度、功耗、成本以及灵活性等方面都具有明显的优势。本文首先简要概述了数字复接技术的发展现状,以及现场可编程门阵列FPGA在通信领域的应用优势。基于数字复接的原理,并根据设计目标,确立了适合本课题的准同步数字复接系统方案。其次,详细描述了系统复接端和分接端各单元电路,包括HDB3编／译码,正码速调整／恢复,位同步、帧同步信号提取,E1／E2信号复接和分接的设计思想及实现方法。重点介绍了作为准同步复接核心部分的正码速调整／恢复模块,对该模块运用Gray码(格雷码)技术进行了优化,解决了FIFO在读写异域时钟下指针传递与比较的难题。在QuartusⅡ集成开发环境下,按照自顶向下的设计原则,完成了系统各单元电路的VerilogHDL语言编写、功能仿真、综合、布局布线、时序仿真等。最后,在各部分功能分别实现的基础上,对E1／E2准同步数字复接系统的核心模块进行了波形的观察与调试,达到了预期的效果。更多还原

【Abstract】 Digital multiplexing is a technology for digital combination which is based on the principle of time-division multiplexing. In the digital communication network, the digital multiplexing is not only a specialized technique that keeps abreast of source coding, digital transmission and digital switching, but also the basis of technologies such as the frame justification in network synchronization, the line multiplexing in the line concentrator and the time-division splicing in digital switching. In recent years, with changes of users’demand and the development of transmission technology, the PDH (Plesiochronous Digital Hierarchy)in optical communication fields is being replaced gradually by the SDH(Synchronous Digital Hierarchy), however, PDH can be designed for different needs of different clients because of its moderate capacity, flexible configuration,low cost,and complete functions,so it has advantages in certain access situations(such as situations that have low demands for transmission capacity).This thesis makes an in-depth research on key technologies of plesiochronous digital multiplexing and demultiplexing, and designs a scheme of four-channel E1 (Europe’s 30-channel pulse code modulation, or called the base group, rate is 2.048Mbps)/E2(the second group, rate is 8.448Mbps) plesiochronous digital multiplexing system based on FPGA according to the actual needs,and the scheme achieves the main functions by single-chip FPGA, this solution has an obvious advantage in integration, power consumption, cost and flexibility,etc.This thesis begins with a brief overview of development status for the digital multiplexing technology, as well as application advantages of field programmable gate array FPGA in the communications field.Based on the principle of digital multiplexing and in accordance with designed objectives, a plesiochronous digital multiplexing system program which is suitable for my subject established. Furthermore,a detailed description of circuits that constituted each module at the multiplexing-side and demultiplexing-side are given, including design ideas and implementation methods of the HDB3 encoding/decoding, positive justification/recovery,bit synchronization and frame synchronization signal extraction, E1/E2 signal multiplexing and demultiplexing.Special emphasis is placed on positive justification and recovery module,which is regarded as core part of the plesiochronous multiplexing, the module is optimized by using Gray-coding technique in FIFO, solved the problem which existed in delivery and comparison of address pointers under the exotic clocks. In integrated development environment of Quartus II,VerilogHDL language programming, the function simulation, synthesis, layout and timing simulation of each unit circuit are completed according to the top-down design principle. Finally, based on the realization of function of each section, the waveform observation and debugging of the core parts in system is carried out, and anticipated effect is achieved.更多还原