【作者】 孔昕；

【导师】 吴武臣；

【作者基本信息】 北京工业大学 ， 微电子学与固体电子学， 2010， 硕士

【摘要】 随着集成电路特征尺寸进入深亚微米阶段,超大规模集成电路(VLSI)中各种互联效应的影响已经变得越来重要。互联线延时(Interconnect delay)、串扰效应(Crosstalk Effect)、电压降效应(IR-Drop)、电子迁移效应(EM Effect)和天线效应(Process Antenna Effect)等问题已经成为了物理设计的瓶颈,制约着集成电路的发展。本文针对上述5种互联效应的起因、危害和解决方法进行了深入的研究,并在互联线延时和串扰方面提出了自己的修复和预防措施。这些修复和预防措施成功地应用到YAK SOC芯片的物理设计中,并保证了芯片时序驱动下的持续收敛和完备的可制造性。本文提出了深亚微米条件下YAK SOC芯片的逻辑综合、物理实现和验证的流程。对标准单元布局、IO布局、时钟树综合、布线等重要的步骤给出了详细的分析,最终成功完成了YAK SOC芯片的物理设计。设计得到的GDSII版图文件,经过验证,满足时序要求和达到预定的电路功能,并通过了DRC和LVS检查,可以交付流片。YAK SOC芯片为本实验室自行开发的SOC芯片,拥有多项自主IP产权,主要应用于蓝牙和RFID的无线通信。采用HJTC的180nm工艺,工作频率为50MHz,芯片面积为3200μm?3300μm。本文的研究结果对于深亚微米工艺下的大规模物理设计与优化,具有一定的指导意义和应用价值。更多还原

【Abstract】 When the development of VLSI technology step into deep-submicron level (DSM), the impact of interconnect effect in VLSI become more important than before. Interconnect delay, Crosstalk Effect, IR-Drop, EM Effect, Process Antenna Effect have become the bottle-neck of the physical design and brings new challenge.Five interconnect effect mentioned above are analyzed detailed in this paper. Method to prevent and fix interconnect effect is used in YAK SOC chip’s design, ensuring the continuous convergence and manufacturability under timing driven.Logic synthesis, physical design and verification of YAK SOC are presented in this paper. Some important process such as floorplanning, IO placement, clock synthesis, routing are analyzed. The physical design of YAK SOC is completed successful. The GDSII layout file could fulfill with the timing requirement and implement the anticipative function. Since DRC and LVS verification process have finished, this layout is able to tape out.YAK SOC is a SOC chip designed by our lab. Its area is 3200μm?3300μm. It use HJTC’s 180nm technology and is operated at 50 MHz. The chip is used in Bluetooth or RFID.The research result of this paper has some directive meaning and applicable value in physical design and optimization for VLSI under deep-submicron technology.更多还原